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touch screen controller ad7877 rev. a in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features 4-wire touch sc reen interface lcd noise reduction feature (s topacq pin) automatic conversion sequen cer and timer user-programmable conversi on parameters on-chip tempe r ature sensor: ?40 c to +8 5c on-chip 2.5 v r e ference on-chip 8-bit dac 3 auxili ary anal og inputs 1 de dicated and 3 o p tio n al gp io s 2 direct batter y meas uremen t channels (0.5 v to 5 v) 3 interrupt out p uts touch-pressur e measur emen t wake up on touch function specified throughput rate of 125 ksps single supply, v cc of 2.7 v to 5 . 25 v separate v dr iv e leve l for seri al interface shutdown mode: 1 a maxi mum 32-lea d lfcsp 5 mm x 5 mm package applic ati o ns personal digita l assistants smart hand-he l d devices touch screen monitors point-of-sale te rminals medical dev i ces cell phones pagers func tio n a l block di agram 19 din 26 dclk 27 dout 28 v drive 18 cs 23 dav control logic and serial port dac register control registers gpio registers alert status/ mask register limit registers limit comparator results registers sequencer 8-bit dac 29 arng 30 aout 4 a ux3/gpio 3 5 a ux2/gpio 2 6 a ux1/gpio1 31 v ref pen interrupt and wake-up on touch 17 penirq alert logic 22 alert stop acq logic 20 stopacq 14 agnd 15 dgnd 21 gpio4 2.5v ref buf to gpio1-3 adc data 12-bit successive approximation adc with track-and-hold clock 9 to 1 i/p mux temperature sensor 2 bat2 battery monitor 3 bat1 battery monitor 11 y? 13 y+ 10 x? 12 x+ 7 v cc ref ? in ref+ dual 3-1 mux x? y? gnd x+ y+ v ref ad7877 03796-001 fi g u r e 1 . general description the ad7877 is a 12-b i t s u cces s iv e a p p r o x ima t ion ad c wi t h a s y nc h r onou s s e r i a l i n t e r f a c e a n d l o w on re s i st a n c e s w itc h e s f o r dr i v in g t o uc h s c r e en s. th e ad7 877 o p era t es f r o m a sin g l e 2.7 v t o 5.25 v p o w e r s u p p l y (f un c t ional o p era t ion t o 2.2v), a nd f e a t ur es thr o ug h p u t r a t e s o f 125 ks ps. th e ad7877 f e a t ur es dir e c t b a t t e r y me as ur emen t on t w o in p u t s , t e m p era t ur e and t o uc h-p r ess u r e m e as ur em en t. the ad7877 als o has a n on-bo a r d r e f e r e n c e o f 2.5 v . w h en n o t in us e , i t can b e s h u t do wn t o con s er v e p o w e r . an ext e r n al r e fer e n c e can a l s o b e a p plie d and can b e va r i e d f r o m 1 v to +v cc , w h i l e t h e a n alog in p u t ran g e is f r o m 0 v t o v ref . t h e de vice in cl udes a sh utdo w n m o de, w h ich r e d u c e s i t s c u r r en t co n s um p t io n t o les s tha n 1 a. t o r e d u ce t h e ef fe c t s o f n o is e f r o m l c d s , t h e acq u isi t io n phas e of t h e on - b o a rd a d c c a n b e c o n t ro l l e d v i a t h e stop a c q pi n . u s er -p r o g r a mma b l e con v ersi o n co n t r o ls i n cl ude va r i a b le acq u isi t ion t i m e a nd f i rst con v e r sio n del a y . u p to 16 a v er a g es ca n b e t a k e n p e r co n v ersio n . th er e is als o a n on- b o a r d d a c fo r l c d backlig h t o r co n t ras t con t r o l . th e ad787 7 ca n r u n in ei t h er s l a v e o r mas t er m o de , usin g a con v ersion s e q u e n cer and timer . i t is ideal f o r ba t t er y-p o wer e d sys t em s s u c h as p e rs o n al dig i t a l as sis t a n ts wi th r e sis t i v e to uc h s c r e en s and o t her p o r t a b le eq ui p m en t . the p a r t is a v a i l a b l e in a 32-le a d le ad f r am e ch i p s c a l e p a ck a g e (lfcs p ).
ad7877 rev. a | page 2 of 44 table of contents specifications ..................................................................................... 3 timing specifications ....................................................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 te r m i no l o g y ...................................................................................... 9 typical performance characteristics ........................................... 10 circuit information ........................................................................ 14 tou ch s c re e n p r i nc ipl e s ............................................................ 14 measuring touch screen inputs ............................................... 15 touch-pressure measurement .................................................. 16 stopacq pin ............................................................................ 16 temperature measurement ....................................................... 17 battery measurement ................................................................. 18 auxiliary inputs .......................................................................... 19 limit comparison ...................................................................... 19 control registers ............................................................................ 20 control register 1 ....................................................................... 20 control register 2 ....................................................................... 21 sequencer registers ................................................................... 22 interrupts ..................................................................................... 24 syncronizing the ad7877 to the host cpu ........................... 25 8-bit dac ........................................................................................ 26 serial interface ................................................................................ 28 wr iting d ata ............................................................................... 28 wr ite timing ............................................................................... 29 reading data ............................................................................... 29 v drive pin ..................................................................................... 29 general-purpose i/o pins ............................................................. 30 gpio configuration .................................................................. 30 grounding and layout ................................................................. 32 pcb design guidelines for chip scale packages ................... 32 register maps .................................................................................. 33 detailed register descriptions ..................................................... 35 gpio registers ........................................................................... 41 outline dimensions ....................................................................... 43 ordering guide .......................................................................... 43 revision history 11/04changed from rev. 0 to rev. a changes to absolute maximum ratings ...................................... 6 changes to figure 4.......................................................................... 7 changes to table 4............................................................................ 7 changes to grounding and layout section ................................ 32 changes to figure 42...................................................................... 32 changes to ordering guide .......................................................... 43 7/04revision 0: initial version
ad7877 rev. a | page 3 of 44 specifications v cc = 2.7 v to 3.6 v, v ref = 2.5 v internal or external, f dclk = 2 mhz, t a = ?40c to +85c, unless otherwise noted. table 1. parameter min typ max unit test conditions/comments adc dc accuracy resolution 12 bits no missing codes 11 12 bits integral nonlinearity 1 2 lsb lsb size = 610 v differential nonlinearity 1 ?0.99/+2 lsb lsb size = 610 v offset error 1 2 6 lsb v cc = 2.7 v gain error 1 4 lsb external reference noise 70 v rms power supply rejection 70 db internal clock ffrequency 2 mhz switch drivers on resistance 1 y+, x+ 14 ? y?, x? 14 ? analog inputs input voltage ranges 0 v ref v dc leakage current 0.1 a input capacitance 30 pf accuracy 0.3 % all channels, internal v ref reference input/output internal reference voltage 2.44 2.55 v internal reference tempco 50 ppm/c v ref input voltage range 1 v cc v dc leakage current 1 a v ref input impedance 1 g? cs = gnd or v cc ; typically 25 ? when on-board reference enabled temperature measurement temperature range ?40 +85 c resolution differential method 2 1.6 c single conversion method 3 0.3 c accuracy differential method 2 4 c single conversion method 3 2 c calibrated at 25c battery monitor input voltage range 0.5 5 v @v ref = 2.5 v input impedance 14 k? sampling, 1 g? when battery monitor off accuracy 1 3.2 % external/internal reference, see figure 25
ad7877 rev. a | page 4 of 44 parameter min typ max unit test conditions/comments dac resolution 8 bits integral nonlinearity 1 bits differential nonlinearity 1 guaranteed monotonic by design voltage mode output voltage range 0 ? v cc /2 v dac register bit 2 = 0, bit 0 = 0 0 ? v cc v dac register bit 2 = 0, bit 0 = 1 slew rate ?0.4, +0.5 v/s output settling time 12 15 s 0 to 3/4 scale, r load = 10 k?, c load = 50 pf capacitive load stability 50 100 pf r load = 10 k? output impedance 75 k? power-down mode short circuit current 21 ma current mode output current range 0 1000 a dac regist er bit 2 = 1, full-scale current is set by r rng output impedance open power-down mode logic inputs input high voltage, v inh 0.7 v drive v input low voltage, v inl 0.3 v drive v input current, i in 1 a typically 10 na, v in = 0 v or v cc input capacitance, c in 4 10 pf logic outputs output high voltage, v oh v drive ? 0.2 v i source = 250 a, v cc /v drive = 2.7 v to 5.25 v output low voltage, v ol 0.4 v i sink = 250 a floating-state leakage current 10 a floating-state output capacitance 4 10 pf output coding stra ight (natural) binary conversion rate conversion time 8 s cs high to dav low throughput rate 125 ksps power requirements v cc (specified performance) 2.7 3.6 v functional from 2.2 v to 5.25 v v drive 1.65 v cc v i cc digital i/ps = 0 v or v cc converting mode 240 380 a adc on, internal reference off, v cc = 3.6 v 650 900 a adc on, internal reference on, v cc = 3.6 v 900 a adc on, internal reference on, dac on static 150 a adc on, but not converting, internal reference off, v cc = 3.6 v shutdown mode 1 a 1 see the section. terminology 2 difference between temp0 and temp1 measurement. no calibr ation necessary. 3 temperature drift is ?2.1 mv/c. 4 sample tested @ 25c to ensure compliance.
ad7877 r e v. a | pa ge 5 o f 4 4 timing specifica t ions t a = t min to t ma x , u n l e s s o t h e r w i s e n o t e d ; v cc = 2.7 v t o 5.25 v , v ref = 2.5 v . sa m p le t e st e d a t 25c t o en s u r e co m p lian ce . al l in p u t sig n als a r e sp e c if ie d wi t h t r = t f = 5 n s (10% t o 90% o f v cc ) and t i me d f r om a vol t age l e vel of 1 . 6 v . table 2. parameter limit at t min , t ma x u n i t d e s c r i p t i o n f dclk 1 10 khz min 20 mhz max t 1 16 ns min cs falling edge to first dclk rising edge t 2 20 ns min dclk high pulse width t 3 20 ns min dclk low puls e wid t h t 4 12 ns min din setup time t 5 12 ns min din hold time t 6 2 16 ns max cs falling edge to dout, three-state disabled t 7 2 16 ns max dclk falling edge to dout valid t 8 3 16 ns max cs rising edge to dout high impedance t 9 0 ns min cs rising edge to dclk ignored 1 mark/ s pace ratio for the dc l k input is 40/60 to 60/40. 2 mea s ure d with the loa d circuit o f a n d d e f i ne d as the time re quire d fo r the o u tput to cro s s 0.4 v or 2.0 v. figu re 3 f i g ure 3. 3 t 8 i s d e ri ved f r om t h e m e a s ur ed t i m e t a ken by t h e da t a o u t p ut s t o ch a n ge 0. 5 v wh en loa d ed wi t h t h e ci rcui t o f th e m e a s ured numbe r i s the n extrapo l ate d back to re mo ve the e f f e cts of charging o r d i s c harging the 50 pf capacito r. this me ans that the ti me , t 8 , quoted in the timing characteri s t ics is the true bus rel i nquis h time of the part and is ind e pe nde nt o f the bus lo ad ing. 03796-004 dclk t 1 t 2 t 3 t 5 t 4 t 6 t 7 t 9 t 8 din msb lsb msb lsb dout 1 2 3 15 16 cs f i gu r e 2 . de tai l e d t i mi n g d i a g r a m
ad7877 r e v. a | pa ge 6 o f 4 4 absolute maximum ra tings t a = 2 5 c , u n l e ss ot he r w i s e not e d. table 3. p a r a m e t e r r a t i n g v cc to gnd ?0.3 v to +7 v analog input voltage to gnd ?0.3 v to v cc + 0.3 v digital input voltage to gnd ?0.3 v to v cc + 0.3 v digital output v o ltage to gnd ?0.3 v to v cc + 0.3 v v ref to gnd ?0.3 v to v cc + 0.3 v input current to any pin except supplies 1 10 ma esd rating 2.5 kv operating temperature range ?40c to +85c storage temperature range ?65c to +150c junction tempe r ature 150c lfcsp package power dissi pati on 450 mw ja thermal impedance 135.7c/w ir reflow peak temperature 220c pb-free parts only 260c (0.5c) lead temperature (soldering 10 s) 300c 1 transient currents of up to 100 ma do not cause s c r latch-up. s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y a nd f u n c t i o n al op era t io n o f t h e de v i ce a t t h es e o r a n y o t h e r con d i t io n s ab o v e t h o s e lis t e d i n t h e op era t io nal s e c t io n s o f t h is sp e c if ic a t ion is n o t i m plie d . e x p o sur e t o ab s o lute m a x i m u m r a t i ng c o nd it i o ns for e x te nd e d p e r i o d s m a y af fe c t d e v i c e rel i a b i l it y . 03796-003 200 ai ol 200 ai oh 1.6v to output pin c l 50pf f i gure 3 . l o a d cir c ui t fo r di g i ta l o u tput t i m i ng sp eci f ic ati o ns esd c a ution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad7877 r e v. a | pa ge 7 o f 4 4 pin conf igura t ion and fu nction descriptions 03796-002 nc 1 bat2 2 bat1 3 a ux3/gpio3 4 a ux2/gpio2 5 a ux1/gpio1 6 v cc 7 nc 8 nc 24 dav 23 alert 22 gpio4 21 stopacq 20 din 19 cs 18 penirq 17 nc v re f aout arng v driv e dout dclk nc 32 31 30 29 28 27 26 25 nc x? y? x+ y+ agnd dgnd nc 9 10 11 12 13 14 15 16 nc = no connect ad7877 top view (not to scale) f i gure 4. pin config ur ation ta ble 4. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic description 1 nc no connect. 2 bat2 battery monitor input. adc inpu t channel 7. 3 bat1 battery monitor input. adc inpu t channel 6. 4 aux3/gpio3 auxiliary analog input. adc inp ut channel 5. ca n be reconfigur ed as gpio pin. 5 aux2/gpio2 auxiliary analog input. adc inp ut channel 4. ca n be reconfigur ed as gpio pin. 6 aux1/gpio1 auxiliary analog input. adc inp ut channel 3. ca n be reconfigur ed as gpio pin. 7 v cc power supply input. the v cc range for the ad78 77 is from 2.2 v to 5.25 v. 8C9 nc no connect. 10 x? touch screen position input. 11 y? touch screen position input. adc input channel 2. 12 x+ touch screen position input. adc input channel 0. 13 y+ touch screen position input. adc input channel 1. 14 agnd analog ground. ground reference point for all analog circuitry on the ad 7877. a ll analog input signals and any external refere n c e signal should be referred to this voltage. 15 dgnd digital ground. ground reference for all digital circui try on the ad7877. all digi tal input signals should be referred to this voltage. 16, 32 nc no connect. 17 penirq pen interrupt. d i gital active low output (h as 50 k ? internal pull-u p resistor) . 18 cs chip select inpu t. active low log i c input. this input pr ovides the dual function of initiating conve r sion s on the ad7877 and enabling the ser i al input/output re gister. 19 din spi? serial data input. data to be written to the a d 7877s registers sh ould be pr ovided on this input and is clock e d into the register on the rising edge of dclk. 20 stopacq stop acquisition pin. a signal a pplied to this pi n can be monitored by the ad78 77, so that acquisition of new data by the adc is halted while t h e signal i s activ e . used to reduc e the effect of n o ise from an lc d screen on the touch screen measurement s . 21 gpio4 dedicated general-pu rpose logic input/ output pin. 22 alert digital active low output. interr upt output, whi c h goes low if a gpio data bit is set, or if the aux1, te mp1, bat1, or bat2 measurements are out of range. 23 dav data available output. active l o w logic output. asserts low when new da ta is available in the a d 7877 results registers. this output is high im pedance when cs is high. 24C25 nc no connect. 26 dclk external clock i n put. logic input. dclk provides the serial c l oc k for accessing data from the part. 27 dout serial data output. logic output. the conversi on result from the ad7877 is provi d ed on this output as a serial data stream. the bits are clocked out on the falling edge of the dclk in put. this output is high i m pedance when cs is high. 28 v drive logic power supply input. t h e voltage supp lie d at this pin determines the op e r ating voltage for the serial interface of the ad7877.
ad7877 rev. a | page 8 of 44 pin no. mnemonic description 29 arng when the dac is in current output mode, a resistor from arng to gnd sets the output range. 30 aout analog output voltage or current from dac. 31 v ref reference output for the ad7877. the inte rnal 2.5 v reference is available on this pin for use external to the device. the reference output must be buffered before it is applied elsewhere in a system. a capacitor of 100nf is strongly recommended between the v ref pin and gnd to reduce system noise effects. alternatively, an external reference ca n be applied to this inp ut. the voltage range for the external reference is 1.0 v to v cc . for the specified performance, it is 2.5 v on the ad7877.
ad7877 rev. a | page 9 of 44 terminology integral nonlinearity the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale (a point 1 lsb below the first code transition), and full scale (a point 1 lsb above the last code transition). differential nonlinearity the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error the deviation of the first code transition (00000) to (00001) from the ideal (agnd + 1 lsb). gain error the deviation of the last code transition (111110) to (111111) from the ideal (v ref ? 1 lsb) after the offset error has been adjusted out. on resistance a measure of the ohmic resistance between the drain and the source of the switch drivers.
ad7877 rev. a | page 10 of 44 typical perf orm ance cha r acte ristics t a = 25c, v cc = 2.7 v , v ref = 2.5 v , f sa m p l e = 125 kh z, f dc l k = 16 f sam p l e = 2 m h z , u n l e ss ot he r w i s e note d. 800 700 600 500 ?50 ? 30 ?10 0 30 50 70 90 03796-030 temperature ( c) curre nt ( a) adc and ref adc, ref, and dac f i gure 5. su p p ly cu rr e n t v s . t e m p er atu r e 1000 400 500 600 700 800 900 2.0 2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 03796-031 v cc (v) curre nt ( a) adc and ref adc, ref, and dac f i gure 6. su p p ly cu rr e n t v s . v cc 0.6 ? 0.6 ? 0.5 ? 0.4 ? 0.3 ? 0.2 ? 0.1 0 0.1 0.2 0.3 0.4 0.5 ? 5 0 ? 3 0 ? 1 0 1 03 05 07 0 9 0 03796-039 temperature ( c) delta from 25 c (ls b ) f i gure 7 . ch a n ge i n adc g a i n vs . t e m p er a t u r e 200 80 100 120 140 160 180 ? 5 0 ? 3 0 ? 1 0 1 03 05 07 0 9 0 03796-032 temperature ( c) curre nt (na) f i gure 8. f u l l p o w e r-d o wn i dd v s . t e mper atu r e 0.6 ? 0.6 ? 0.5 ? 0.4 ? 0.3 ? 0.2 ? 0.1 0 0.1 0.2 0.3 0.4 0.5 ? 5 0 ? 3 0 ? 1 0 1 03 05 07 0 9 0 03796-040 temperature ( c) delta from 25 c (ls b ) f i gure 9. ch ange in a d c o ffset v s . t e m p er atu r e 1.0 ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 0 500 1000 1500 2000 2500 3000 3500 4000 03796-044 code inl (lsb) f i g u re 10. a c d inl p l ot
ad7877 rev. a | page 11 of 44 1.0 ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 0 500 1000 1500 2000 2500 3000 3500 4000 03796-045 code dnl (ls b ) f i g u re 11. a d c dn l plot 22 8 10 12 14 16 18 20 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 03796-048 v dd (v) r on ( ? ) y+ to v dd y ? to gnd x+ to v dd x? to gnd f i gure 12. s w itch o n r e sistance v s . v cc (x+, y + : v cc to p i n ; x?, y ? : pin to g nd) 22 8 10 12 14 16 18 20 ? 4 0 ? 2 0 0 2 04 06 08 0 03796-049 temperature ( c) r on ( ? ) y+ to v dd y? to gnd x+ to v dd x? to gnd f i gure 13. s w itch o n r e sistance v s . t e mpe r atu r e (x+, y + : v cc to p i n; x?, y ? : pin to g nd) 16 14 12 10 8 6 4 2 0 ?50 9 0 70 50 30 10 ?1 0 ?3 0 03796-046 temperature ( c) re fe re nce curre nt ( a) f i gure 14. e x ter n a l r e fer e n c e cu rrent v s . t e mpe r atu r e 2.520 2.515 2.510 2.505 2.500 2.495 2.490 2.485 2.480 2.475 ? 5 0 ? 3 0 ? 1 0 1 03 05 07 0 9 0 03796-033 temperature ( c) v re f (v ) f i gure 15. inte rn al v ref v s . t e mper ature 2.508 2.496 2.498 2.500 2.502 2.504 2.506 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 03796-034 v cc (v) v re f (v ) f i gure 16. inte rn al v ref vs . v cc
ad7877 rev. a | page 12 of 44 3145 3135 3125 3115 3105 3095 3085 3075 3065 3055 3045 ? 5 0 ? 3 0 ? 1 0 1 03 05 07 0 9 0 03796-041 temperature ( c) adc code (de c i ma l) f i g u r e 1 7 . a d c c o de v s . t e m p e r a t u r e (2 . 7 v s u ppl y ) 1183 1176 1177 1178 1179 1180 1181 1182 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 03796-042 v cc (v) te mp 1 code f i g u re 18. t e mp 1 v s . v cc 982 975 976 977 978 979 980 981 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 03796-043 v cc (v) te mp 0 code f i g u re 19. t e mp 0 v s . v cc 03796-047 inte rnal v ref (v ) turn-on time ( s) 0 3 6 20 40 60 80 100 120 ?20 0 no cap 0.711 s settling time 100nf cap 54.64 s settling time f i gure 20. inte rn al v ref v s . t u rn- o n t i me 10 ? 150 ? 130 ? 110 ?90 ?70 ?50 ?30 ?10 0 10k 20k 30k snr 70.25db thd 78.11db 40k 03796-035 frequency inp u t tone amplitude (db) f i g u re 21. t y pic a l f f t pl ot f o r t h e aux i l i ar y ch ann e ls of t h e a d 7 8 7 7 at 9 0 kh z s a mpl e rate and 1 0 kh z inp u t f r equ e nc y 3.50 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 0123456789 1 0 03796-036 source/sink current (ma) dac o/p level (v) dac o/p source ability dac o/p sink ability f i gure 22. d a c s o u r c e and sink curr ent c a pab i lit y
ad7877 rev. a | page 13 of 44 03796-037 ch1 200mv ch2 100mv m2.00 s ch1 780mv 1 ? : 144mv @: 1.296v v dd = 3v temperature = 25 c f i gure 2 3 . d a c o / p s e ttl ing ti me (z ero s c al e t o ha l f - s c a l e ) 600 500 400 300 200 100 0 0 2 5 5 0 7 5 100 125 150 175 200 225 250 03796-038 input code (decimal) dac s i nk curre nt ( a) dac sink current f i gure 24. d a c s i nk current v s . input code ?2 ?1 0 1 2 03796-050 error (%) f i gure 25. t y pic a l a c cur a c y for b a tter y chann e l ( 2 5 c )
ad7877 rev. a | page 14 of 44 circuit i n forma t ion the ad7877 is a co m p lete , 12-b i t da t a acq u is i t io n sys t em f o r dig i t i zin g p o si tio n al in p u ts f r o m a t o uch s c r een in p d a s and o t h e r devices. i n addi tion, i t can m o ni t o r tw o ba t t er y v o l t a g es, amb i e n t t e m p e r a t u r e, a n d t h re e a u x i l i ar y an a l o g volt age s , w i t h h i g h a n d l o w l i m i t c o m p ar i s on s on t h re e of t h e i n put s , a n d h a s u p t o f o ur g e n e ral-p u r p os e log i c i/o p i n s . the co r e o f th e ad7877 is a hig h s p e e d , lo w p o w e r , 12-b i t a n alog-t o-d i g i ta l co n v er t e r (ad c ) wi t h in p u t m u l t i p lex e r , o n -ch i p t r ack - and- h o ld , an d on -chi p clo c k. t h e r e su l t s o f co n v ersio n s a r e s t o r e d in 11 r e su l t s r e g i s t ers, and the r e s u l t s f r om one a u x i l i ar y i n put a n d t w o b a tte r y i n put s c a n b e co m p a r e d wi th hig h and lo w limi ts s t o r e d in limi t r e g i st ers t o ge ne r a te a n out - of - l i m it aler t . th e ad7877 als o co n t a i n s lo w r e sis t a n c e a n alog swi t ch es t o s w i t c h t h e x and y exci ta tio n v o l t a g es t o t h e to uch s c r e en, a st o p a c q p i n to co n t r o l t h e ad c ac q u isi t ion p e r i o d , 2.5 v r e fer e n c e , o n -ch i p t e m p era t ur e s e n s o r , a nd 8-b i t d a c t o con t r o l l c d con t ras t . the hig h s p eed s p i s e r i a l b u s p r o v ides co n t r o l of, a nd co m m uni c a t ion wi t h , t h e de vice. o p era t ing f r o m a sin g le s u p p l y f r o m 2.2 v t o 5 v , th e ad7877 o f f e rs thr o ug h p u t ra t e s o f u p t o 125 kh z. th e device is a v a i la b l e in a 5 mm b y 5 mm 32-lead lead f r a m e chi p s c ale p a c k a g e . the da t a ac q u isi t io n sys t em o f t h e ad7877 has a n u m b er o f ad van c e d fe a t ures: ? i n p u t cha n nel s e q u ence d a u toma t i c a l l y o r s e le c t e d b y th e h o s t ? s t o p a c q fe a t ur e t o r e d u ce no is e f r o m l c d ? a v e r ag i n g of f r om 1 to 1 6 c o n v e r s i ons f o r noi s e re d u c t i o n ? pr og ra mma b l e acq u isi t ion t i m e ? po w e r m a n a g e m e n t ? pr o g ra mma b l e ad c p o w e r - u p del a y b e fo r e f i rst co n v ersio n ? c h oi c e of i n te r n a l or e x te r n a l r e f e re nc e ? c o n v ersio n a t p r ep r o g r a m m e d in t e r v als t o uch scr een principles a 4- wir e t o uch s c r e en co n s ists o f tw o f l exi b le , t r a n s p a r en t, r e s i s t i v e - c o at e d l a y e r s t h at a r e n o r m a l l y s e p a r a t e d b y a s m a l l a i r ga p . t h e x la yer has co nd uc t i ve ele c t r o d es r u nnin g do w n t h e le ft a n d ri gh t e d g e s, allo w i n g th e a p p l ica t i o n o f a n e x ci ta ti o n v o l t a g e acr o s s t h e x l a yer f r o m lef t t o r i g h t. 03796-005 x+ x? y? y+ conductive electrode on bottom side plastic film with transparent, resistive coating on bottom side plastic film with transparent, resistive coating on top side lcd screen conductive electrode on top side f i g u re 26. bas i c co ns t r uc t i on of a t o u c h s c reen the y l a yer has co nd uc t i ve ele c t r o d es r u nnin g a l o n g t h e to p a n d bo t t o m e d ge s, allo w i n g th e a p p l i c a t i o n o f a n e x ci ta ti o n v o l t a g e down t h e la yer f r o m t o p t o b o t t om. prov i d e d t h a t t h e l a y e r s are of u n i f or m re s i st iv it y , t h e vo lt age at an y p o i n t b e t w e e n t h e t w o el e c t r o d e s i s prop or t i on a l to t h e h o riz o n t al posi t i o n f o r th e x la y e r a n d th e v e r t i c al posi ti o n f o r th e y la y e r . w h en t h e s c r een is t o uch e d , t h e tw o l a yers mak e con t ac t. i f o n l y t h e x l a yer is ex ci t e d , t h e v o l t a g e a t t h e p o in t o f co n t ac t, and t h er efo r e t h e h o r i zo n t al p o si t i on, can b e s e n s e d a t on e o f t h e y la yer e l e c t r o d es. simi la rl y , if onl y t h e y la yer is exci t e d , t h e v o l t a g e , and t h e r efo r e t h e v e r t ic al p o si t i o n , c a n b e s e n s e d a t one o f th e x e l ectr od e s . b y sw i t c h in g al t e rn a t e l y betw ee n x a n d y exci t a t i on and m e as ur in g t h e v o l t a g es, t h e x a nd y co o r di- na t e s o f t h e co n t ac t p o i n t c a n b e fo un d . i n ad di t i on to m e a s ur in g t h e x an d y co o r di na tes, i t is a l s o p o s s i b le t o est i ma t e t h e t o uch p r es s u r e b y m e as ur in g t h e co n t ac t r e sis t ance betw een t h e x an d y la yers. the ad7877 is de s i g n e d to f a c i l i t a te t h i s me a s u r e m e n t . f i gur e 28 s h o w s a n eq u i valen t cir c ui t o f th e ana l og in p u t s t r u c t ur e o f th e ad7877, sh o w in g th e t o uc h s c reen s w i t ch es, the ma in analog m u l t i p lexer , t h e a d c wi t h a n alog a nd dif f er en t i al re f e re nc e i n put s , and t h e du a l 3 - to - 1 m u lt ip l e x e r t h a t s e l e c t s t h e re f e re nc e s o u r c e f o r t h e a d c .
ad7877 rev. a | page 15 of 44 aux3/gpio4 bat1 bat2 aux2/gpio3 aux1/gpio2 12-bit successive approximation adc with track-and-hold 9 to 1 i/p mux temperature sensor y? y+ x? x+ v cc ref? in+ ref int/ext ref+ dual 3-1 mux x? y? gnd x+ y+ v ref 03796-006 f i gure 27. a n a l og i n put struc t ure the ad7877 can b e s e t u p t o co n v er t s p ecif ic in p u t c h a n n e ls or t o co n v er t a s e q u en ce o f c h a n ne ls a u t o ma tical l y . th e r e s u l t s o f t h e ad c con v e r sio n s a r e s t o r e d in t h e r e s u l t s r e g i s t ers. s e e t h e se ri al i n t e rf a c e secti o n f o r d e ta il s . w h en m e as ur ing t h e an ci l l a r y a n alog in p u ts (a ux1 t o a u x3, b a t1 and b a t2), th e ad c us es th e in t e r n al r e f e r e n c e , o r a n ext e r n al r e fer e n c e a p plie d t o t h e v ref p i n, an d t h e m e asur e m en t is r e f e r r ed t o gnd . measuring t o uch scr een input s w h en m e as ur ing t h e t o uch s c r e en i n p u ts, i t is p o s s i b le t o m e as ur e usi n g t h e in t e rn al (o r ext e rn al) r e f e r e n c e , o r t o use th e t o uch s c r e en exci t a t i o n v o l t a g e as t h e r e fer e n c e a nd p e r f o r m a ra t i om et r i c, dif f er en t i a l m e as urem e n t. the dif f er en t i a l m e t h o d is t h e def a u l t and is s e le c t e d b y cle a r i n g t h e s e r/ df r bit (b i t 11) in c o n t r o l reg i s t er 1. th e sin g le-en d ed m e t h o d is se l e ct e d b y se t t in g th i s b i t . single-ended method t h e s i ng l e - e nd e d me t h o d i s i l lu st r a te d for t h e y p o s i t i on i n f i gur e 28. f o r th e x p o si t i on, t h e exci t a t i on v o l t a g e w o u l d b e a p plie d to x+ and x? and t h e vol t a g e m e a s ur e d a t y+. 03796-007 adc ref+ input (via mux) x+ ref? touch screen y+ y? gnd v ref v cc f i gure 28. sing l e -e nded con v ers i on o f t o uc h s c reen inp u ts the v o l t a g e s e e n a t t h e in p u t t o t h e ad c in f i g u r e 28 is v in = v cc ytotal y r r ? (1) the ad v a n t a g e o f t h e sin g le- e nde d m e t h o d is t h a t t h e t o uch s c r e en exci t a t i on v o l t a g e can b e swi t ch e d o f f o n ce th e sig n al has been a c q u i r ed . b e ca us e a scr een ca n d r a w o v e r 1 m a , th i s i s a sig n if ica n t co n s idera t ion fo r a b a t t e r y -p o w er e d sy st em. the dis a d v an t a ges o f t h e sin g le -ende d m e t h o d a r e as fol l o w s: ? i t ca n be us e d onl y if v cc is close t o v ref . i f v cc is g r e a t e r t h a n v ref , s o m e p o si t i o n s o n t h e s c r e en a r e o u tside t h e ra n g e o f th e a d c . i f v cc is les s tha n v ref , t h e f u l l ra n g e of t h e a d c is not ut i l i z e d . ? the r a t i o o f v cc to v ref m u s t be kn o w n. i f v ref a nd/o r v cc v a r y r e la ti v e t o o n e a n o t h e r , th is ca n i n tr o d uce e r r o r s . ? v o l t a g e dr o p s acr o s s t h e s w i t ches ca n in t r o d uc e er r o rs. t o uch s c r e en s can ha ve a t o tal end-t o -end r e sis t an ce of f r o m 200 ? t o 900 ?. t aking th e lo w e s t s c reen r e sis t an ce of 200 ? a n d a typ i cal s w i t ch resis t a n ce o f 14 ?, this co u l d r e d u ce t h e a p p a r - en t exci t a tio n vol t a g e t o 200/22 8 100 = 87% o f i t s ac t u al v a l u e . i n a d d i ti o n , th e v o l t a g e d r o p a c r o s s th e lo w - si d e swi t ch adds t o t h e a d c in p u t v o l t a g e . this i n t r o d uce s a n o f fs et in t o t h e i n put vol t ag e, w h i c h me ans t h a t it c a n ne ve r re ach ze ro . the sin g le- e n d e d m e t h o d is a d e q ua t e fo r a p pli c a t io n s in w h ich t h e i n p u t d e vi ce is a fa irly b l u n t a nd i m p r e c is e i n st r u m e n t such as a f i n g er . ratiomet ric m e thod t h e ra tio m etr i c m e t h o d is ill u s t ra t e d in f i gur e 29. h e r e , th e n e ga ti v e i n p u t o f th e ad c r e f e r e n c e i s ti ed t o y? a n d th e posi ti v e in p u t i s co n n e ct e d t o y+, so th e scr e e n e x ci ta ti o n v o l t a g e p r o v ide s t h e r e fer e nce fo r t h e a d c. the in p u t o f t h e a d c i s c o n n e c t e d to x + to d e te r m i n e t h e y p o s i t i on. 03796-008 adc ref+ input (via mux) ref ? v cc x+ touch screen y+ y? gnd f i gure 29. rat i o m e t ric con v e r s i on of t o uch s c r e en i n puts
ad7877 rev. a | page 16 of 44 f o r gr ea t e r accurac y , th e ra tio m etr i c m e t h o d has tw o sign if ican t ad van t a g e s : ? the r e fer e n c e to t h e a d c is p r o v ide d f r o m t h e ac t u al v o l t a g e a c r o s s th e sc r een , so v o l t a g e d r o p s a c r o s s th e sw i t c h e s h a v e no e f fe c t . ? b e ca us e t h e m e as ur emen t is r a t i o m et r i c, i t do es n o t ma t t er if t h e v o l t a g e acr o s s t h e s c r e en v a r i es in t h e lo ng t e r m . h o w e v e r , i t m u st n o t c h an g e a f t e r t h e sig n al has be e n ac q u ir e d . t h e d i sad v a n t a g e o f th e ra ti o m e t ri c m e t h od i s th a t t h e scr een m u s t b e p o w e r e d u p al l t h e t i me , b e ca us e i t p r o v ides t h e r e fer e n c e v o l t a g e fo r t h e a d c. t o uch-pressure measurement the p r es s u r e a pplie d t o t h e t o u c h s c r e en v i a a p e n o r f i n g er can als o be m e as ur e d wi th t h e ad7 877 usin g s o m e sim p le calc u l a - tio n s. th e con t ac t r e sis t a n c e b e tw e e n t h e x an d y p l a t es is me a s u r e d . t h i s prov i d e s a go o d i n d i c a t i o n of t h e s i z e of t h e dep r es s e d a r e a a n d , t h er efo r e , t h e a p plie d p r es sur e . th e a r e a o f t h e s p ot tou c he d i s prop or t i on a l to t h e s i z e of t h e o b j e c t t o uc hin g i t . th e size o f this r e sista n ce (r tou c h ) ca n be calc ula t ed usin g tw o dif f er en t m e t h o d s. first method the f i rs t m e t h o d r e q u ir es t h e us er t o kn o w t h e t o t a l r e sis t an ce o f t h e x - pl a t e t a b l et (r x ). thr e e t o uch s c r e en c o n v ersio n s a r e re qu i r e d : ? m e as ur emen t of t h e x p o si t i o n , x pos i ti o n (y+ in p u t). ? m e as ur emen t of t h e y? i n p u t wi t h t h e exci t a t i o n v o l t a g e a p plie d to y+ and x? (z1 m e a s ur em en t). ? m e as ur emen t of t h e x+ i n p u t wi t h t h e exci t a t i o n v o l t a g e a p plie d to y+ and x? (z2 m e a s ur em en t). th e s e t h r e e m e as ur emen t s a r e i l l u s t ra t e d i n f i gur e 30. the ad7877 has tw o s p ec ial ad c c h a n ne l s e t t in gs tha t co nf igur e t h e x a nd y s w i t ch es fo r z1 a nd z2 me as ur emen t an d store t h e re su l t s in t h e z1 and z 2 re su l t s re g i ste r s . the z1 m e as ur em en t is ad c cha n n e l 1010b , an d t h e res u l t is s t o r e d in th e r e g i st er wi t h re ad a ddr es s 11010b . th e z2 m e as ur em en t is ad c chann e l 0 010b , an d t h e r e s u l t is s t o r e d in th e r e g i st er wi t h read a d dr es s 1 0010b . the t o uc h r e sis t a n c e can t h en b e calc u l a t e d usin g th e f o l l o w ing eq ua ti o n : r to uch = ( r xp la t e ) ( x pos i t i o n /40 96 [ z2 / z1 ) ? 1] (2) 03796-009 y? y+ x? x+ touch resistance measure z1 position x? x+ y? y+ touch resistance measure x position y? y+ x? x+ touch resistance measure z2 position f i gure 30. th r e e m e asure m ents r e qu i r ed f o r t o u c h pr ess u r e secon d m e tho d the s e cond m e t h o d r e q u ir es t h a t t h e r e sis t an c e o f t h e x-pl a t e a nd y - pl a t e t a b l ets b e k n o w n. thr e e t o uch s c r e en con v ersio n s a g a i n a r e r e q u ire d , a m e as ur emen t o f t h e x p o s i t i o n ( x pos i ti o n ), y p o si t i o n ( y pos i ti o n ), a n d z1 p o si tio n . t h e f o l l ow i n g e q u a t i on a l s o c a l c u l a t e s t h e tou c h re s i st a n c e : r to uch = r xpl a t e ( x pos i t i o n /409 6) [(4096/ z1 ) ? 1] ? r ypl a t e [1 ? ( y pos i t i o n /4096)] (3) st op a c q pi n a s explaine d p r e v i o u s l y , t o uch s c r e en s a r e com p os e d o f tw o r e sis t i v e la yers, n o r m al l y place d o v er a n l c d s c r e en. b e c a us e t h es e la yers a r e in clos e p r o x imi t y t o t h e l c d s c r e en, n o is e can b e co u p le d f r o m t h e s c r e en on t o t h es e r e sis t i v e la yers, ca usin g er r o rs in t h e t o uch s c r e en p o si t i o n al m e as ur e m en ts. f o r exa m p l e , a ji t t e r mig h t be n o ticea b le in t h e cur s o r o n - s c r e en. i n m o s t l c d t o uc h s c r e en sys t e m s, a sig n al , s u c h as an l c d in v e r t sig n al o r o t h e r co n t r o l sig n al , is p r e s en t, and n o is e is us ual l y co u p led o n t o the t o uc h s c r e en d u r i n g this sig n al s ac ti ve p e r i o d , a s s h ow n i n fi g u re 3 1 . 03796-010 lcd signal touch screen signal noisy period noisy period f i gure 31. l c d n o is e affec t s t o uch s c reen m e asu r e m ents
ad7877 rev. a | page 17 of 44 it is only during the sample or acquisition phase of the ad7877s adc operation that noise from the lcd screen has an effect on the adcs measurements. during the hold or conversion phase, the noise has no effect, because the voltage at the input of the adc has already been acquired. therefore, to minimize the effect of noise on the touch screen measurements, the adc acquisition phase should be halted. the lcd control signal should be applied to the stopacq pin. to ensure that acquisition never takes place during the noisy period when the lcd signal is active, the ad7877 monitors this signal. no acquisitions take place when the control signal is active. any acquisition that is in progress when the signal becomes active is aborted and restarts when the signal becomes inactive again. to accommodate signals of different polarities on the stopacq pin, a user-programmable register bit is used to indicate whether the signal is active high or low. the pol bit is bit 3 in control register 2, address 02h. setting pol to 1 indicates that the signal on stopacq is active high; setting pol to 0 indicates that it is active low. pol defaults to 0 on power-up. to disable monitoring of stopacq, the pin should be tied low if pol = 1, or tied high if pol = 0. under no circumstances should the pin be left floating. the signal on stopacq has no effect while the adc is in conversion mode, or during the first conversion delay time. (see the control registers section for details on first conversion delay.) when enabled, the stopacq monitoring function is imple- mented on all input channels to the adc: aux1, aux2, bat1, bat2, temp1, and temp2, as well as on the touch screen input channels. temperature measurement two temperature measurement options are available on the ad7877: the single conversion method and the differential conversion method. the single conversion method requires only a single measurement on adc channel 1000b. differential conversion requires two measurements, one on adc channel 1000b and a second on adc channel 1001b. the results are stored in the results registers with addresses 11000b (temp1) and 11001b (temp2). the ad7877 does not provide an explicit output of the temperature reading. some external calculations must be performed by the system. both methods are based on an on-chip diode measurement. single conversion method the single conversion method makes use of the fact that the temperature coefficient of a silicon diode is approximately ?2.1 mv/c. however, this small change is superimposed on the diode forward voltage, which can have a wide tolerance. it is, therefore, necessary to calibrate by measuring the diode voltage at a known temperature to provide a baseline from which the change in forward voltage with temperature can be measured. this method provides a resolution of approximately 0.3c and a predicted accuracy of 2.5c. the temperature limit comparison is performed on the result in the temp1 results register, which is simply the measurement of the diode forward voltage. the values programmed into the high and low limits should be referenced to the calibrated diode forward voltage to make accurate limit comparisons. an example is shown in the limit comparison section. differential conversion method the differential conversion method is a 2-point measurement. the first measurement is performed with a fixed bias current into a diode (when the temp1 channel is selected), and the second measurement is performed with a fixed multiple of the bias current into the same diode (when the temp2 channel is selected). the voltage difference in the diode readings is proportional to absolute temperature and is given by the following formula: ? v be = ( kt / q ) (1 n n ) (4) where: v be represents the diode voltage. n is the bias current multiple (typical value for ad7877 =120). k is boltzmanns constant. q is the electron charge. this method provides a resolution of approximately 1.6c, and a guaranteed accuracy of 4c without calibration. determina- tion of the n value on a part-by-part basis improves accuracy. assuming a current multiple of 120, which is a typical value for the ad7877, taking boltzmanns constant, k = 1.38054 10 ?23 electrons v/k, the electron charge q = 1.602189 10 ?19 , then t , the ambient temperature in kelvin, would be calculated as follows: ? v be = ( kt / q ) (1 n n ) t k = (? v be q)/(k 1n n) = ? v be 1.602189 10 ?19 )/(1.38054 10 ?23 4.65) t c = 2.49 103 ? v be ? 273 ? v be is calculated from the difference in readings from the first conversion and second conversion. the user must perform the calculations to get ? v be , and then calculate the temperature value in degrees. figure 32 shows a block diagram of the temperature measurement circuit.
ad7877 rev. a | page 18 of 44 03796-011 temp1 temp2 mux adc i v be 105 i f i g u re 32. bl ock d i ag r a m of t e m p er at ur e m e as u r e m e n t circuit tem p er at ur e c a lc ulations i f a n explici t te m p er a t ur e r e ad i n g in c is r e q u i r e d , t h e n t h is ca n b e calc u l a t e d as fol l o w s fo r t h e sin g l e me asur em en t me t h o d : 1. c a lc u l a t e t h e s c ale fac t o r o f t h e ad c i n deg r e e s p e r ls b: d e g r ees pe r l s b = ad c ls b s i z e / ? 2.1 mv = v ref /4096)/ ? 2. 1 mv 2. sa ve t h e a d c ou t p ut d cal a t t h e calib r a t io n t e m p er a t ur e t cal . 3. ta k e a d c r e a d i n g d am b at t e mp e r at u r e t o b e m e a s u r e d t am b . 4. c a lc u l a t e t h e di f f er en ce in deg r e e s b e tw e e n t cal a nd t am b usin g ? t = ( d am b ? d cal ) deg r ees pe r l s b 5. a dd ? t to t cal . ex a m p l e : t h e i n te r n a l 2 . 5 v re f e re nc e i s u s e d . 1. d e g r ees pe r l s b = (2.5/4096)/ ? 2.1 10 ? 3 = ? 0. 291. 2. the ad c o u t p u t is 983 decimal a t 25c, e q ui val e n t t o a dio d e fo r w a r d vol t a g e o f 0.6 v . 3. the a d c o u t p ut a t t am b is 880. 4. ? t = (880 ? 98 3) ? 0.291 = 30. 5. t am b = 25 + 30 = 55c. t o calc u l a t e t h e t e m p era t ur e explici t l y usin g t h e dif f er en t i al me t h o d : 1. c a lc u l a t e t h e l s b size o f t h e a d c in v : ls b = v ref /409 6 2. su bt r a c t tem p 1 fr o m te mp2 a nd m u l t i p ly b y ls b siz e to ge t ? v be . 3. m u l t i p l y b y 2490 a nd s u b t rac t 2 73 t o g e t th e t e m p er a t ur e in c. ex a m p l e : t h e i n te r n a l 2 . 5 v re f e re nc e i s u s e d . 1. ls b s i ze = 2.5 v/4096 = 6.1 10 ? 4 v (610 v). 2. te mp1 = 880 and te mp2 = 11 03: ? v be = (1103 ? 880) 6.1 10 ? 4 = 0.136 v 3. t = 0.136 2490 ? 273 = 65c. ba t t er y measurement the ad7877 can m o ni t o r ba t t er y v o l t a g es f r o m 0.5 v t o 5 v o n tw o in p u ts, b a t1 a nd b a t2. f i g u r e 33 sh o w s a b l o c k di a g ra m o f a b a t t er y v o l t a g e m o ni t o r e d t h r o ug h t h e b a t1 p i n. th e v o l t a g e t o t h e v cc p i n o f th e ad7877 is ma in t a ined a t t h e desir e d s u p p l y vol t a g e vi a t h e dc /dc r e gu l a t o r w h i l e t h e in p u t t o t h e r e gu l a t o r is m o n i t o r e d . this v o l t a g e on b a t 1 is di v i de d do wn b y 2 i n t e r n al l y , s o t h a t a 5 v b a t t er y v o l t ag e is p r es en te d to th e ad c as 2.5 v . t o co ns er v e p o w e r , th e divider cir c ui t is o n o n l y d u r i n g t h e s a m p ling o f a vol t a g e on b a t1. the b a t2 in put cir c ui t r y is iden t i ca l. the b a t1 in p u t is ad c cha n ne l 0110b and the r e s u l t is s t o r e d in reg i st er 10110b . th e b a t2 in p u t is ad c cha nne l 0111b and th e r e s u l t is s t o r ed in reg i s t er 1 0111b . 03796-012 adc 0.25v?2.5v sw bat1 v cc v ref 5k ? 5k ? dc-dc converter battery 0.5v to 5v f i g u re 33. bl ock d i ag r a m of b a t t er y m e as ure m ent c i rc uit f i gur e 33 s h o w s th e ad c usin g th e in t e r n al r e f e r e n c e o f 2.5 v . i f a dif f er en t r e fer e n c e v o l t a g e is us e d , t h e n t h e maxim u m ba t t er y v o l t a g e t h a t t h e ad7877 ca n m e as ur e c h a n g e s. th e max i m u m vol t age m e asura b le i s v ref 2, b e ca us e t h is v o l t a g e g i v e s a f u l l -s c a le o u t p u t f r o m t h e ad c. i f a smal ler r e f e r e n c e is us e d , s u ch as 2 v , t h e n t h e max i m u m b a t t er y v o l t a g e m e as ura b le is 4 v . i f a la rg er r e f e r e n c e is us e d , s u c h as 3.5 v , th en the max i m u m b a t t e r y vol t a g e m e a s ura b le is 7 v . t h e in ter n a l r e fer e n c e is p a r t ic u l a r ly sui t e d fo r us e w h e n m e asur in g l i -i on b a t t er ies, w h er e t h e mini m u m vol t a g e is ab o u t 2 . 7 v a nd t h e m a x i m u m i s ab out 4 . 2 v . a pro p e r choi c e of e x te r n a l re f e re nc e en s u r e s tha t o t her v o l t a g e ra n g es ca n be acco mm o d a t e d .
ad7877 rev. a | page 19 of 44 auxiliary inputs the ad7877 has three auxiliary analog inputs, aux1 to aux3. these channels have a full-scale input range from 0 v to v ref . the adc channel addresses for aux1 to aux3 are 0011b, 0100b, and 0101b, and the results are stored in registers 10011b, 10100b, and 10101b. these pins can also be reconfigured as general-purpose logic inputs/outputs, as described in the gpio configuration section. limit comparison the aux1 measurement, the two battery measurements, and the temp1 measurement can all be compared with high and low limits, and an out-of-limit result made to generate an alarm output at the alert pin. the limits are stored in registers with addresses from 00100b to 01011b. after a measurement from any one of the four channels is converted, it is compared with the corresponding high and low limits. an out-of-limit result sets one of the status bits in the alert status/enable register. for details on these and other registers, see the register maps and detailed register descriptions sections. for details on writing and reading data, see the serial interface section. as mentioned previously, the temperature comparison is made using the result of the temp1 measurement, which is the diode forward voltage. because the temperature coefficient of the diode is known but the actual forward voltage can have a wide tolerance, it is not possible to program the high and low limit registers with predetermined values. instead, it is necessary to calibrate the temperature measure- ment, calculate the temp1 readings at the high and low limit temperatures, and then program those values into the limit registers, as follows: 1. calculate lsb per degree = ? 2.1 mv/( v ref /4096). 2. save the calibration reading d cal at calibration temperature t cal . 3. subtract t cal from limit temperatures t high and t low to get the difference in degrees between the limit temperatures and the calibration temperature. 4. multiply this value by lsb per degree to get the value in lsbs. 5. add these values to the digital value at the calibration temperature to get the digital high and low limit values. example: the internal 2.5 v reference is used. 1. t high = +65c and t low = ? 10c. 2. lsb per degree = ? 2.1 10 ? 3 /(2.5/4096) = ? 3.44. 3. d cal = 983 decimal at 25c. 4. d high = (65 ? 25) ? 3.44 + 983 = 845. 5. d low = ( ? 10 ? 25) ? 3.44 + 983 = 1103.
ad7877 rev. a | page 20 of 44 control registers c o n t r o l reg i st e r 1 co n t a i ns t h e ad c chann e l addr es s, t h e se r / df r b i t (t o ch o o s e sin g le o r dif f er en tial m e t h o d s o f t o uc h s c r e en m e as ur em e n t), t h e r e g i st er r e ad addr es s , a n d t h e a d c m o de b i ts. c o n t r o l reg i s t er 1 sho u ld al wa ys be t h e las t reg i s t er t o be p r og ra mm e d p r io r t o s t ar tin g co n v ersion s. i t s p o w e r - o n d e fa ul t val u e is 00h. t o c h an g e a n y p a ram e t e r af t e r co n v er sio n has b e gun, t h e p a r t s h o u ld f i rs t be p u t in t o m o de 00, th e c h a n g e s made , and th e n c o n t r o l reg i st er 1 r e p r og ra mm e d , en s u r i n g tha t i t is al wa ys the last r e g i s t er t o be p r og ra mm ed befo r e con v ersio n s b e g i n. 03796-013 ser/ dfr chnl add 3 chnl add 2 chnl add 1 chnl add 0 rd add 4 rd add 3 rd add 2 rd add 1 rd add 0 adc mode 1 adc mode 0 11 0 f i g u re 34. cont r o l r e g i s t er 1 c o n t ro l r e g i s t e r 2 s e t s t h e t i me r , re f e re nc e, p o l a r i t y , f i r s t co n v ersio n del a y , a v er a g ing, and acq u isi t io n t i m e . i t s p o w e r - on defa u l t v a l u e is 00h. s e e t h e d e t a i l e d reg i st er d e s c r i p t io n s s e c t io n fo r m o re info r m a t io n on t h e co n t r o l r e g i st ers. 03796-014 avg 1 avg 0 acq 1 acq 0 pm 1 pm 0 fcd 1 fcd 0 pol ref tmr 1 tmr 0 11 0 f i g u re 35. cont r o l r e g i s t er 2 co n t r o l r e g i s t e r 1 adc mode (c ontrol register 1 bits <1:0>) th es e b i ts s e lec t th e o p era t in g m o de o f th e ad c. the ad7877 has t h r e e o p er a t in g m o des. th e s e a r e s e le c t e d b y wr i t in g t o t h e m o de b i ts in c o n t r o l reg i s t er 1. i f t h e m o de b i t s a r e 00, n o co n v ersio n is p e r f o r m e d . ta ble 5. co nt rol regi s t er 1 m o de sel e ct i o n mode 1 mode 0 function 0 0 do not convert (default) 0 1 single-channel conver sion, ad7 877 in slave m o d e 1 0 sequence 0, ad7877 in slave m o de 1 1 sequence 1, ad7877 in master mode i f th e m o de b i ts a r e 01, a sin g le co n v ersio n is p e r f o r m e d on t h e c h a n n e l s e le c t e d b y wr i t in g t o t h e c h ann e l b i ts o f c o n t r o l reg i st er 1 (bi t s 7 t o 10). a t t h e end o f t h e con v ersio n , if t h e t m r b i ts in c o n t r o l reg i st er 2 a r e s e t t o 00, t h e m o de b i ts r e v e r t t o 00 a n d th e a d c r e t u rn s t o n o co n v e r t m o de un ti l a ne w con v ersio n is ini t i a t e d b y t h e h o st. s e t t in g t h e t m r b i ts t o a val u e o t h e r t h a n 00 c a us es t h e co n v ersio n t o b e r e p e a t e d , as des c r i b e d i n t h e t i m e r (c o n t r ol reg i ster 2 bi ts <1:0>) s e c t ion. the f l o w c h a r t in f i gur e 37 sh o w s h o w t h e ad7877 o p era t es in m o de 01. the ad7877 can als o be p r og rammed t o con v er t a s e q u en ce o f s e lec t e d c h a n nels a u t o ma tical l y . the tw o m o des f o r this typ e o f co n v ersio n a r e sla v e m o de and mas t er m o de . f o r s l a v e m o de o p era t ion, t h e cha n n e ls t o b e di g i t i ze d a r e s e le c t e d b y s e t t in g t h e co r r es p o n d in g b i ts in s e q u en cer reg i st er 0. c o n v ersio n is ini t i a te d b y wr i t in g 10 b t o t h e mo de b i t s o f c o n t r o l r e gi s t e r 1 . t h e a d c th e n d i gi ti z e s th e s e l e ct ed cha n n e ls an d s t o r es t h e r e s u l t s i n t h e co r r es p o ndin g r e s u l t s r e g i s t ers. a t t h e end o f t h e con v ersio n , if t h e tmr b i ts i n c o n t r o l reg i st er 2 a r e s e t t o 00, th e m o de b i ts rev e r t t o 00 an d t h e ad c r e t u r n s t o n o con v er t m o de un t i l a ne w co n v ersio n is ini t i a t e d b y t h e h o st. s e t t in g t h e t m r b i ts t o a c o de o t h e r t h a n 00 ca us es t h e con v ersio n s e q u e n ce t o b e r e p e a t e d . th e f l o w cha r t in f i gur e 38 sh o w s h o w t h e ad7877 o p era t es in m o de 10. f o r mas t er m o de o p era t ion, t h e cha n n e ls t o b e dig i t i ze d a r e wr i t t e n t o s e q u en cer reg i st er 1 . m a s t er m o de is t h e n s e le c t e d b y wr i t in g 11 t o th e m o de b i ts in c o n t r o l reg i st er 1. i n this m o de , t h e wa k e -u p o n t o uch fe a t ur e is ac t i v e , s o co n v ersio n do es n o t beg i n immedia t e l y . the ad7877 wa i t s un til t h e s c r een is t o uch e d b e fo r e b e g i nnin g t h e s e q u e n ce o f con v ersio n s. the a d c th e n d i gi ti z e s th e s e l e ct ed c h a n n e l s , a n d th e r e s u l t s a r e wr i t t e n t o the r e s u l t s r e g i s t ers. th e ad7877 wa i t s f o r th e s c r e en t o be t o uch e d aga i n, o r f o r a tim e r ev en t if th e s c r e en r e ma in s tou c he d, b e f o re b e g i n n i ng a n ot he r s e qu e n c e of c o n v e r s i ons . f i gur e 39 is a f l o w c h a r t, s h o w in g h o w t h e ad7877 o p era t es in m o de 11. adc cha nnel ( c ont r ol r egis t er 1 bits < 1 0:7>) the ad c c h ann e l is s e lec t ed b y b i ts 10:7 o f c o n t r o l reg i s t er 1 (ch a d d 3 t o ch ad d0). i n addi tio n , the s e r/ df r b i t, bi t 11, s e le c t s b e tw e e n sin g le-e n d e d and dif f er en t i al con v ersio n . a co m p let e list o f c h a n n e l addr es s e s is g i v e n in t a b l e 6. f o r m o de 0 (sing l e-cha n nel) co n v ersio n , t h e ch a nnel is s e le c t e d b y wr i t in g t h e a p p r o p r i a t e ch ad d3 t o ch a d d0 co de t o co n t r o l r e g i s t e r 1 . f o r s e q u en t i a l cha n n e l con v ersi o n , cha n n e ls t o b e con v er t e d a r e s e le c t e d b y s e t t in g b i ts co r r es p o n d in g t o t h e cha nne l n u m b er in s e qu e n c e r r e g i ste r 1 f o r sl a v e mo d e s e qu e n c i ng or s e qu e n c e r reg i st er 2 fo r mas t er m o de s e quen cing. f o r bo th si n g le -c h a nn e l a n d se q u e n ti al co n v e r si o n , n o rm al (s i n gl e - en d e d ) co n v e r s i o n i s se l e ct ed b y c l ea ri n g th e s e r / df r b i t in c o n t r o l r e g i st er 1. r a t i om et r i c (dif fer e n t ia l) con v ersio n is se l e ct e d b y se t t in g th e s e r / df r bi t .
ad7877 rev. a | page 21 of 44 table 6. codes for selecting input channel and normal or ratiometric conversion channel ser/ dfr chadd(3:0) analog input x switches y switches +ref ?ref 0 0 0 0 0 0 x+ (y position) off on y+ y? 1 0 0 0 0 1 y+ (x position) on off x+ x? 2 0 0 0 1 0 y? (z2) x+ off, x? on y+ on, y? off y+ x? 3 0 0 01 1 aux1 off off v ref gnd 4 0 0 1 00 aux2 off off v ref gnd 5 0 0 1 0 1 aux3 off off v ref gnd 6 0 0 1 1 0 bat1 off off v ref gnd 7 0 0 1 1 1 bat2 off off v ref gnd 8 0 1 0 0 0 temp1 off off v ref gnd 9 0 1 0 0 1 temp2 off off v ref gnd 10 0 1 0 1 0 x+ (z1) x+ off, x? on y+ on, y? off y+ x? - 0 1 0 1 1 invalid address - 0 1 1 0 0 invalid address - 0 1 1 0 1 invalid address - 0 1 1 1 0 invalid address - 0 1 1 1 1 invalid address 0 1 0 0 0 0 x+ (y position) off on v ref gnd 1 1 0 0 0 1 y+ (x position) on off v ref gnd 2 1 0 0 1 0 y? (z2) x+ off, x? on y+ on, y? off v ref gnd 3 1 0 0 1 1 aux1 off off v ref gnd 4 1 0 1 0 0 aux2 off off v ref gnd 5 1 0 1 0 1 aux3 off off v ref gnd 6 1 0 1 1 0 bat1 off off v ref gnd 7 1 0 1 1 1 bat2 off off v ref gnd 8 1 1 0 0 0 temp1 off off v ref gnd 9 1 1 0 0 1 temp2 off off v ref gnd 10 1 1 0 1 0 x+ (z1) x+ off, x? on y+ on, y? off v ref gnd - 1 10 1 1 invalid address - 1 1 1 0 0 invalid address - 1 1 1 0 1 invalid address - 1 1 1 1 0 invalid address - 1 1 1 1 1 invalid address control register 2 timer (control register 2 bits <1:0>) the tmr bits in control register 2 enable the adc to repeatedly perform a conversion or conversion sequence either once only or at intervals of 512 s, 1.024 ms, or 8.19 ms. in slave mode, the timer starts as soon as the conversion sequence is finished. in master mode, the timer starts at the end of a conver- sion sequence only if the screen remains touched. if the touch is released at any stage, then the timer stops and, the next time the screen is touched, a conversion sequence begins immediately. table 7. control register 2 timer selection tmr1 tmr0 function 0 0 convert only once (default) 0 1 every 1024 clocks (512 s) 1 0 every 2048 clocks (1.024 ms) 1 1 every 16,384 clocks (8.19 ms) int/ext reference (control register 2 bit <2>) if the ref bit in control register 2 is 0 (default value), the internal reference is selected. if any connection is made to v ref while the internal reference is selected (for example, to supply a reference to other circuits), it should be buffered. an external power supply should not be connected to this pin while ref is equal to 0, because it might overdrive the internal reference. note also that, because the internal reference is 2.5 v, it operates only with supply voltages down to 2.7 v. below this value an external reference should be used. if the ref bit is 1, the v ref pin becomes an input and the internal reference is powered down. this overrides any setting of the pm bits with regard to the reference. an external reference can then be applied to the ref pin.
ad7877 rev. a | page 22 of 44 stopacq pol arity (control register 2 bit <3>) this b i t sh o u l d b e s e t acco r d i n g t o t h e p o la r i ty o f t h e sig n a l a p p l ie d t o t h e s t o p a c q p i n. i f tha t sig n al is ac ti v e hig h , tha t is, no a c qu i s it i o ns shou l d o c c u r du r i ng t h e s i g n a l s h i g h p e r i o d , th en the po l b i t s h o u l d b e s e t to 1. i f th e sig n al is ac ti v e lo w , th en the po l b i t s h o u l d b e 0. th e defa u l t val u e f o r po l is 0. first conv ersi on del a y (control register 2 bits <5:4> ) the f i rs t con v ersio n dela y (fc d ) b i ts i n c o n t rol reg i st er 2 p r og ra m a dela y o f 500 n s (defa u l t ), 128 s, 1.024 m s , o r 8.19 m s b e fo r e t h e f i rs t co n v ersio n , t o a l lo w t h e ad c t i m e t o p o w e r u p . this de l a y als o o c c u rs bef o r e co n v ersio n o f t h e x and y co o r dina te chan n e ls, to a l lo w ex t r a t i m e fo r s c r e en s e t t ling, an d a f t e r t h e last con v ersio n i n a s e q u en c e , t o p r e c ha rg e pe ni rq . i f t h e sig n a l on t h e s t op a c q p i n is b e in g m o n i to r e d and go es ac ti v e d u r i n g t h e fcd , i t is ig n o r e d un til a f t e r t h e fc d p e r i o d . table 8. first conversion d e lay selection f c d 1 f c d f u n c t i o n 0 0 1 clock delay (500 ns) 0 1 256 clocks delay (128 s) 1 0 2048 clocks delay (1.024 ms) 1 1 16,384 clocks de lay (8.19 ms) power management (control regis t er 2 b i ts <7: 6 >) the p o w e r ma na g e m e n t (pm) b i ts in c o n t r o l reg i st er 2 al lo w t h e p o w e r ma nag e m e n t fe a t ur es o f t h e a d c t o b e p r og ra mm e d . i f th e pm b i t s a r e 00, th e ad c is po w e r e d d o wn pe rm a n en tl y . this o v er r i des a n y s e t t in g o f t h e m o d e b i ts i n c o n t r o l reg i st er 1. i f t h e pm b i ts a r e 01 , t h e a d c and t h e r e fer e nce bo th po w e r d o wn w h en th e ad c i s n o t co n v er ti n g . i f th e pm b i ts a r e 10, t h e ad c and r e fer e n c e a r e p o w e r e d u p co n t in uo u s l y . i f t h e pm b i ts ar e 11, t h e a d c, b u t n o t t h e r e fe r e n c e , p o w e rs do wn w h en t h e ad c is n o t con v er t i n g . ta ble 9. power ma na geme nt s e lect i o n pm1 pm0 function 0 0 power d o wn co ntinuously ( d e fault) 0 1 power down ad c and reference when adc is not converting (powers up with fcd at start of c o nversi on) 1 0 powered up continuously 1 1 power down ad c when adc is not converting (powers up with fcd at start of convers i on) acquisition time (control r e gister 2 bits <9:8>) the a c q b i ts i n c o n t r o l r e g i st er 2 al lo w t h e s e le c t io n o f acq u isi t ion tim e s f o r th e ad c of 2 s (defa u l t ), 4 s, 8 s, o r 16 s. th e us er ca n p r og ra m t h e ad c w i t h a n acq u isi t ion t i m e su it a b l e f o r t h e t y p e of s i g n a l b e i n g s a m p l e d. for e x am pl e, sig n als wi t h la rge r c tim e con s t a n t s mig h t r e q u ir e lo n g er acq u isi t ion t i m e s. table 10. acqu isit ion time selection a c q1 a c q0 fu nction 0 0 4 clock periods (2 s) 0 1 8 clock periods (4 s) 1 0 16 clock pe riods (8 s) 1 1 32 clock pe riods (16 s) av eraging (control regi ster 2 bits <11:10>) sig n als f r o m t o uch s c r e en s c a n b e ext r e m e l y no isy . the a v g b i ts in c o n t r o l reg i st er 2 al lo w m u l t i p le con v e r sio n s t o be p e r f o r m e d o n e a ch i n p u t ch a n nel an d a v er a g e d to r e d u ce n o is e. a sin g le con v ersio n can be s e le c t e d ( n o a v er a g in g), whic h is t h e defa u l t, o r 4, 8, o r 16 co n v ersio n s can b e a v erag ed . onl y the f i nal a v e r age d re su lt i s w r itte n i n to t h e re su lt s re g i st e r . table 11. a v er aging selection avg1 avg0 functio n 0 0 adc performs 1 average per channel 0 1 adc performs 4 averages per channel 1 0 adc performs 8 averages per channel 1 1 adc performs 16 averages per channe l sequencer registers ther e a r e tw o s e q u encer r e g i s t ers o n th e ad7 877. s e q u encer r e gi s t e r 0 co n t r o l s th e m e a s ur em en t s p e rf o r m e d d u ri n g a s l a v e m o de s e q u en c e . s e q u en cer reg i s t er 1 co n t r o ls th e m e as ur e- me n t s p e r f or me d d u r i ng a m a s t e r mo d e s e qu e n c e . t o i n cl ude a m e as ur emen t in a s l a v e m o de o r mas t er m o de seq u en c e , t h e r e l e v a n t b i t m u s t be set in s e q u en c e r r e gi s t e r 0 o r s e q u en cer reg i s t er 1. s e t t in g b i t 11 in cl udes a m e as ur em en t o n ad c c h an n e l 0 in t h e s e q u ence, w h ich is t h e y p o si t i o n a l m e as ur em en t. s e t t in g b i t 10 in cl udes a m e as ur em en t on ad c c h a n n e l 1 ( x + m e a s u r e m e n t ) , a n d s o o n , t h r o u g h b i t 1 f o r cha n n e l 10. f i g u r e 36 il l u s t ra t e s th e co r r es p o nden c e between t h e b i ts in t h e s e q u encer r e g i s t ers a nd t h e va r i o u s m e as ur e- m e n t s. b i t 0 in bo th s e q u en cer r e g i s t ers is n o t us ed . s e e als o t h e de ta il e d re gi s t e r de scri p t i o n s secti o n . 03796-015 y+ x+ z2 aux 1 aux 2 aux 3 bat 1 bat 2 temp 1 temp 2 z1 not used 11 0 f i gure 36. s e q u encer r e g i ster
ad7877 rev. a | page 23 of 44 03796- 016 limit comparison start fcd timer update alert enable/status register convert selected channel is fcd finished? host programs ad7877 in mode 01 no yes no yes no yes yes no yes no is averaging finished? once-only mode? write result to registers goto mode 00 alert source enabled? is acquisition time finished? timer finished? is fcd required? start acquisition timer start timer out-of-limit? assert alert output* yes no no yes yes no *note: see explanation in text is stopacq signal active? no is stopacq signal active? no yes yes f i g u re 37. sing le c h ann e l o p er at i o n 03796-017 yes no once-only mode? goto mode 00 timer finished? start timer no yes *note: see explanation in text limit comparison start fcd timer update alert enable/status register convert selected channel is fcd finished? host programs ad7877 in mode 10 no yes no yes no yes yes no is averaging finished? write result to registers alert source enabled? is acquisition time finished? is fcd required? start acquisition timer out-of-limit? assert alert output* yes no yes no vali d sequenc e 0? select next channel goto mode 00 last channel in sequence? yes no yes is stopacq signal active? no yes is stopacq signal active? yes no no f i gure 38. sl ave m o de s e quencer o p er atio n
ad7877 rev. a | page 24 of 44 03796-018 yes no once-only mode? timer finished? start timer no yes *note: see explanation in text limit comparison start fcd timer update alert enable/status register convert selected channel is fcd finished? no yes no yes no yes yes no is averaging finished? write result to registers alert source enabled? is acquisition time finished? is fcd required? start acquisition timer out-of-limit? assert alert output* yes no yes no valid sequence 1? select next channel goto mode 00 last channel in sequence? yes is screen touched? no yes yes no is stopacq signal active? is stopacq signal active? no yes yes no is screen still touched? yes is screen still touched? yes no no no host programs ad7877 in mode 11 f i gure 3 9 . ma st er mo de s e qu enc e r o p er a t i o n interrupt s dat a a v aila ble o u tp ut ( dav ) the da t a a v a i lab l e o u t p u t ( da v ) indic a tes t h a t ne w ad c d a t a is a v a i la b l e i n t h e r e s u l t s r e g i s t ers. w h i l e t h e ad c is idle o r is co n v er ting, da v is hig h . o n ce t h e a d c has f i nishe d co n v er tin g a nd n e w da t a h a s b e en wr i t te n to t h e r e su l t s re g i sters, da v go e s lo w . t akin g da v l o w to re a d t h e re g i ste r s re s e t s da v to a h i g h co ndi t i on. da v is a l so r e s e t, if a ne w co n v ersio n is st a r t e d b y th e ad7877 be c a us e t h e tim e r exp i r e d . th e h o st s h o u l d a t t e m p t to re ad t h e re su lts re g i ste r s on ly w h i l e da v is lo w . 03796-019 cs dav ad7877 s tatus idle setup by host adc converting new data available host reads results idle t conv f i g u re 40. o p er at i o n of da v ou t p u t da v is us ef u l as a host in t e r r u p t i n mast er m o d e . i n t h is m o d e , th e h o s t ca n p r ogra m th e ad 7877 t o a u t o ma ticall y pe rf o r m a s e q u e n ce o f con v ersio n s, a nd can b e in ter r u p te d b y da v at t h e e n d of e a ch c o n v e r s i on s e qu e n c e . w h en t h e on- b o a r d t i mer is p r o g ra mm e d to p e r f o r m a u to m a t i c co n v ersio n s, a li mi t e d t i me is a v a i la b l e t o t h e h o s t t o r e ad t h e r e s u l t s r e g i s t ers befo r e an o t h e r s e q u ence o f co n v ersio n s beg i n s . the da v s i g n a l i s res e t h i g h w h e n t h e t i m e r e x pi re s , and t h e ho st s h ou l d not ac c e ss t h e re su l t s re g i ste r s w h i l e da v is hig h . f i gur e 41 s h o w s th e w o r s t- ca se ti m i n g s f o r r e a d i n g th e r e s u l t s re g i ste r s af te r da v has g o ne lo w . the tim e r is s e t a t a minim u m, a nd t h e con v ersio n s e q u e n c e i n cl udes al l e l e v e n p o s s i b le ad c chan nel s . t 1 i s th e tim e ta k e n f o r a c q u i s i t i o n a n d co n v e r si o n o n one a d c ch an n e l. t 2 sh o w s the minim u m t i m e r de l a y , which is 1024 c l o c k p e r i o d s. t 3 i s th e t i m e ta k e n t o r e a d all 11 r e s u l t r e g i s t ers. i f t h e h o s t w a n t s t o r e ad a l l 1 1 re g i ste r s , t h e n it m u st d o so be f o r e th e ti m e r e x p i r e s. t 4 is t h e max i m u m t i m e a l lo wa b l e bet w een da v go in g lo w a n d t h e h o st b e g i nn in g to re ad t h e re su lt s re g i ste r s . i f t 4 i s e x ceed ed , th e n all r e gi s t er s ca nn o t be r e ad b e fo r e t h e st a r t o f a ne w c o n v ersio n , and i n co r r e c t d a t a co u l d be r e ad b y th e h o s t . 03796-020 dout ad7877 s tatus channel 11 conversion and acquisition timer interval chnl 1 t 1 t 2 t 3 t 4 cs dav f i gure 41. t i m i ng f o r r e ads a f te r da v goes l o w
ad7877 rev. a | page 25 of 44 if f dc l k = 20 mh z (maxim u m ), t h e n t dc l k = 50 n s . t 2 = ti m e r i n t e r v a l t dc l k = (102 4 50 n s ) = 51.2 s t wri t e = t read = 16 c l k p e r i o d t dc l k = 800 n s t 3 = max i m u m t i me t a k e n to wr i t e r e a d addr ess a nd r e ad 11 r e g i s t ers = 800 n s (wr i te) + [800 n s (r ead) 11] = 9.6 s. t 4m a x = t 2 ? t 3 = 51.2 s ? 9.6 s = 41.6 s pen interrupt ( penirq ) the p e n i n t e r r u p t r e q u es t o u t p u t ( pe ni rq ) g o e s l o w wh en ev e r th e scr een i s t o uc h e d . th e pe n in t e rr u p t eq ui v a le n t o u t p u t cir c ui t r y is o u t l in e d i n f i gur e 4 2 . this is a d i g i t a l log i c o u t p u t wi t h an in t e r n al p u l l -u p r e sis t o r o f 50 k?, whic h m e a n s i t do es not ne e d a n e x t e r n a l pu l l - u p . t h e pe ni rq output i d l e s h i g h . the pe ni rq cir c ui tr y is al wa ys ena b le d , excep t d u r i n g co n v ersio n s. 03796-021 x+ touch screen y+ 50k ? y? x ? penirq enable penirq v cc v cc f i g u re 42. pe nir q o u tput equiv a lent cir c u i t w h e n t h e scr een i s t o uch e d , pe ni rq g o es lo w . this can b e us e d t o g e n e ra te a n i n t e r r u p t r e q u es t t o t h e h o s t . w h en t h e s c r e en to uch e nds, pe ni rq g o es hig h i mme dia t e l y , if t h e ad c is id le . i f t h e a d c is con v er t i ng, pe ni rq g o es hig h w h en t h e ad c b e com e s i d le . th e pe ni rq o p era t i o n fo r t h es e tw o co ndi t i on s is sho w n i n f i gur e 4 3 . 03796- 022 s creen penirq adc status touched not touched not touched not touched not touched adc idle s creen penirq adc status touched adc idle adc converting adc idle release not detected penirq detects release penirq detects release penirq detects touch penirq detects touch f i g u re 43. pe nir q o p er at i o n f o r a d c id le an d a d c co nver t i ng sy ncr o nizing the ad7 877 t o the host cpu the tw o s u g g es ted m e t h o d s f o r syn c hr o n izin g t h e ad7877 t o i t s h o s t cp u a r e s l a v e m o de , in w h ich t h e mo de b i ts can b e ei t h er 01b o r 10b , an d mas t er mo de , in w h ich t h e m o de b i t s a r e 11b . in s l av e m o d e , pe ni rq ca n be us e d as an in t e r r u p t t o th e h o s t . wh e n pe ni rq g o es lo w t o indic a t e t h a t t h e s c r e e n has b e en t o uch e d , t h e h o s t is a w a k e n e d . the h o s t can t h en p r og ra m t h e ad7877 t o beg i n con v er tin g in ei ther mo de 01 b o r 10b , an d can r e ad t h e r e s u l t r e g i s t ers a f t e r t h e co n v ersio n s ha v e com p let e d . in m a s t e r m o d e , da v ca n als o b e us ed as an in t e r r u p t t o the h o s t . h o w e v e r , th e h o s t sh o u l d f i rs t ini t ial i ze t h e ad7877 in m o de 11b . the h o s t c a n t h en go in t o s l eep m o de t o co n s er v e p o w e r . th e wa k e -u p o n t o uc h f e a t ur e o f t h e ad7877 is ac ti v e in th i s m o d e , so , w h en th e scr e e n is t o uc h e d , th e p r ogra m m ed s e qu e n c e of c o n v e r s i ons b e g i ns a u tom a t i c a l l y . w h e n t h e da v sig n al as s e r t s, the h o s t r e ads t h e ne w da ta a v ail a b l e in t h e ad7877 r e s u l t s r e g i s t ers an d r e t u r n s t o s l eep mo de . this m e t h o d can sig n if ican t l y r e d u c e t h e lo ad on t h e h o st .
ad7877 rev. a | page 26 of 44 8-bit da c the ad7877 f e a t ur es an o n -c hi p 8-b i t d a c f o r l c d co n t ras t co n t r o l . the d a c can b e co nf ig ur ed f o r v o l t a g e o u t p u t b y c l ea r i n g b i t 2 o f th e d a c r e g i s t er (a ddr es s 111 0b), o r f o r c u r r e n t output by s e tt i n g t h i s b i t . the o u t p u t v o l t a g e ra n g e can b e s e t t o 0 ? v cc /2 b y c l ea ri n g bit 0 of t h e d a c re g i ste r , or to 0 ? v cc b y s e t t in g this b i t. i n c u r r en t m o de , t h e o u t p ut ra n g e is s e le c t a b le b y a n ext e r n al re s i stor , r rn g , co nn e c te d b e twe e n t h e a r n g p i n an d g n d . t h is se t s th e full - s cal e o u t p u t cu rr e n t a c c o r d i n g t o th e f o ll o w i n g eq ua ti o n s : i fs = v cc /( r rn g 6) so r rn g = v cc /( i fs 6) i n c u r r en t m o de , t h e d a c sin k s c u r r en t, t h a t is , p o si t i v e c u r r en t f l o w s in t o g r o u nd . th e maxim u m o u t p u t c u r r en t is 1000 a. the d a c is u p da t e d b y wr i t ing t o a ddr es s 11 10b o f t h e d a c r e g i s t er . the 8 ms bs o f t h e da t a -w o r d a r e us e d fo r d a c da t a . the m o s t ef fe c t i v e w a y t o co n t rol l c d co n t r a s t wi t h t h e d a c i s t o us e i t t o con t r o l t h e fe e d b a ck lo o p o f t h e dc- d c co n v er t e r t h a t s u p p lies t h e l c d b i as v o l t a g e , as s h own in f i gu r e 44. th e b i as v o l t a g e fo r g r a p hic l c d s is typ i cal l y in t h e ra n g e o f 20 v t o 25 v , a nd t h e dc Cdc con v er ter usua l l y has a fe e d b a ck lo o p t h a t a t t e n u a t es t h e ou t p ut v o l t a g e and co m p a r es i t w i t h an i n t e r n al re f e re nc e vo lt ag e. 03796-023 dc-dc converter v fb v out to lcd 8-bit dac ad7877 arng r rng 1 gnd notes: 1 r rng is required only if dac is in current mode. 2 r1 is required only if dac is in voltage mode. aout r1 2 i out r3 r2 comp vref f i gure 4 4 . usi n g th e d a c to a d just l c d c o nt r a st the cir c ui t op era t es as fol l o w s. i f t h e d a c is in c u r r en t m o de w h en t h e d a c o u t p ut is zer o , i t has n o ef fe c t on t h e fe e d b a ck l o op . i r re sp e c t i ve of w h a t t h e d a c d o e s , t h e f e e d b a c k l o op ma in t a in s t h e vol t a g e acr o ss r4 , v fb , e q u a l t o v ref , a nd t h e output vo lt ag e v ou t is v ref ( r2 + r3 )/ r3 a s t h e d a c o u t p u t i s in cr ea se d , i t in cr ea se s t h e f eed ba ck c u r r en t, s o t h e vol t a g e acr o s s r2 a n d , t h er efo r e , t h e o u t p ut v o l t a g e als o i n cr e a s e . n o t e t h a t t h e v o l t a g e acr o ss r3 do es n o t cha n ge . this is i m p o r t a n t fo r ca lc u l a t io n o f t h e ad j u st m e n t ra n g e . i n c u r r en t m o de , i t is q u i t e e a sy t o calc u l a t e t h e r e sis t o r val u es t o g i v e t h e r e q u ir e d ad j u s t m e n t ra n g e in v ou t : 1. f i nd t h e r e q u ir e d max i m u m and min i m u m va lues o f v ou t f r o m t h e l c d ma n u fac t ur er s da t a . 2. d e cide on t h e c u r r en t a r o u n d t h e fe e d b a ck lo op , w h ich fo r re a s on abl e a c c u r a c y of t h e output vo lt age s h ou l d b e at l e a s t 100 tim e s t h e in p u t b i as c u r r en t o f th e dcCdc con v er t e r s co m p a r a t o r . 3. c a lc u l a t e r3 usi n g t h e fol l o w ing e q u a t i o n : r3 = v fb / i fb = v ref / i fb 4. c a lc u l a t e r2 fo r t h e mini m u m v a l u e o f v ou t , w h e n t h e da c h a s n o e f f e c t : r2 = r3 ( v ou t ( m i n ) ? v ref )/ v ref 5. b e ca us e t h e v o l t a g e acr o s s r3 do es n o t cha n g e , s u b t rac t v ref fr o m v ou t m a x a nd v ou tm in to get t h e max i m u m and mini m u m volt ages acr o ss r2. 6. c a lc u l a t e t h e cha n g e i n fe e d b a ck c u r r en t b e tw e e n mini m u m an d max i m u m o u tpu t vol t a g es: ? i = v r2(m a x ) / r2 ? v r2( m in ) / r2 this is t h e r e q u i r e d f u l l -s ca le c u r r en t o f t h e d a c. 7. ca l c u l a t e r rn g f r o m th e eq ua ti o n gi v e n p r e v i o us l y . ex a m p l e : 1. v cc = 5 v . v ou t ( m i n) is 20 v a nd v ou t ( m a x) is 25 v . v ref is 1.25 v . 2. al lo w 100 a a r o u n d t h e f e e d b a c k lo o p . 3. r3 = 1.25 v/100 a = 12.5 k?. u s e t h e nea r es t p r ef er r e d val u e o f 12 k? a nd r e calc u l a t e t h e fe e d b a ck c u r r en t as i fb = 1.25 v/12 k? = 104 a 4. r2 = (20 v ? 1.25 v)/104 a = 180 k?. 5. ? i = 23.75 v/18 0 k? ? 18.75 v/180 k? = 28 a. 6. r rn g = 5 v/(6 28 a) = 30 k?. i n v o l t a g e m o de, t h e cir c ui t op e r a t io n dep e n d s o n w h et h e r t h e maxim u m o u t p u t v o l t a g e o f t h e d a c exce e d s t h e dc Cdc co n v er t e r v ref . w h en t h e d a c o u t p ut v o l t a g e is zer o , i t si nks t h e maxim u m c u r r en t t h r o ug h r1. the fe e d b a ck c u r r en t, a n d , t h er efo r e , v ou t a r e a t t h eir max i m u m. a s t h e d a c o u t p ut v o l t ag e in cr e a s e s, t h e sink c u r r en t and , t h er efo r e , t h e fe e d b a ck c u r r en t de cr e a s e , and
ad7877 rev. a | page 27 of 44 v out falls. if the dac output exceeds v ref , it starts to source current, and v out has to further decrease to compensate. when the dac output is at full scale, v out is at its minimum. note that the effect of the dac on v out is opposite in voltage mode to that in current mode. in current mode, increasing dac code increases the sink current, so v out increases with increasing dac code. in voltage mode, increasing dac code increases the dac output voltage, reducing the sink current. calculate the resistor values as follows: 1. decide on the feedback current as before. 2. calculate the parallel combination of r1 and r3 when the dac output is zero: r p = v ref / i fb 3. calculate r2 as before, but use r p and v outmax : r2 = r p ( v out(max) ? v ref )/ v ref 4. calculate the change in feedback current between minimum and maximum output voltages as before using ? i = v r2(max) / r2 ? v r2(min) / r2 this is equal to the change in current through r1 between zero output and full scale, which is also given by ? i = current at zero ? current at full scale = v / r1 ? ( v ref ? v )/ r1 = v / r1 5. r1 = v fs /? . 6. calculate r3 from r1 and r using r3 = ( r1 r p )/( r1 ? r p ) example: 1. v cc = 5 v and v fs = v cc . v out(min) is 20 v and v out(max) is 25 v. v ref is 1.25 v. allow 100 a around the feedback loop. 2. r p = 1.25 v/100 a = 12.5 k?. 3. r2 = 12.5 k? (25 ? ? 1.25 ?)/1.25 ? = 237 k?. use nearest preferred value of 240 k?. 4. ? i = 25 v/240 k? ? 20 v/240 k? = 21 a. 5. r1 = 5 v/21 a = 238 k?. use nearest preferred value of 250 k?. 6. r3 = (180 k? 12.5 k?)/(180 k? ? 12.5 k?) =13.4 k?. use nearest preferred value of 13 k?. the actual adjustment range using these values is 21 v to 26 v.
ad7877 rev. a | page 28 of 44 serial interf ace the ad7877 is co n t r o l l ed via a 3-wir e s e r i al p e r i p h eral in t e r f ac e (s p i ). t h e s p i has a da ta in p u t p i n (d in) f o r in p u t t in g da ta t o th e de vi ce , a da t a o u t p u t p i n (d o u t ) f o r r e a d in g da t a ba ck f r o m th e de vi ce , a n d a da ta c l o c k p i n (d clk ) f o r c l o c ki n g da t a in to and o u t o f t h e d e vice. a ch i p -s ele c t p i n ( cs ) ena b les o r d i sa b l e s t h e se rial i n t e rfa c e . writing d a t a da t a is wr i t t e n to th e ad7877 in 16-b i t w o r d s. the f i rs t f o ur b i ts o f th e w o rd a r e th e r e g i st er addr es s, whic h te l l s th e ad7877 w h ich reg i s t er to wr i t e t o . th e n e xt 12 b i ts a r e da t a . h o w t h e ad7877 han d les th e da ta b i ts dep e n d s o n t h e reg i s t er addr es s. reg i st er a d dr ess 0000b is a d u mm y addr es s, w h ic h do es n o thin g. reg i st er addr es s e s f r o m 0010b t o 111 0b a r e 12-b i t r e g i s t ers tha t p e r f o r m va r i o u s fun c tio n s as des c r i be d in t h e re g i ste r m a p . reg i st er a d dr ess 1111b is n o t a p h ysical r e g i st er , b u t enab les a n ext e n d e d wr i t i n g m o de t h a t a l lo ws wr i t in g t o t h e gpi o co nf igura t io n r e g i s t ers. w h en t h e r e g i s t er addr es s is 1111b , the n e xt fo ur b i ts o f t h e da t a -w o r d a r e t h e addr es s o f a gp i o co nf igura t io n r e g i s t er an d t h e ei g h t ls bs a r e t h e gp i o co nf igu- ra ti o n da ta . f o r d e ta ils o n t h e co n f i g ura t i o n o f th e gp i o p i n s , s e e t h e g e n e ral - pur p os e i/o p i n s s e c t ion. reg i st er a d dr ess 0001b is a ph ysical r e g i s t er , c o n t r o l reg i s t er 1, b u t t h is is a sp e c ia l r e g i ster . i t co n t a i n s da t a fo r s e t t i n g u p t h e ad c chann e l and o p era t in g mo de , b u t bi ts 20 t o 6 a r e t h e r e g i s t er addr es s fo r r e adin g. th e s e def i n e w h ich r e g i s t er is r e ad b a ck d u r i ng t h e ne x t re a d o p e r a t i o n . c o n t ro l r e g i ste r 1 shou l d b e t h e las t reg i s t er in t h e a d 787 7 t o b e p r og ra mm e d b e fo r e s t a r ti n g a co n v er s i o n . t h e th r ee t y pe s o f da t a - w o r d s used f o r w r it i n g are s h ow n i n fi g u re 4 5 . 03796-024 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16-bit data-word wadd3 wadd2 wadd1 wadd0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 writing to a register 12 bits data 4-bit register write address 1 1 1 1 eadd3 eadd2 eadd1 eadd0 d7 d6 d5 d4 d3 d2 d1 d0 extended write operation to gpio registers 8 bits gpio data 4-bit extended address 0 0 0 0 ser/dfr chadd3 chadd2 chadd1 chadd0 radd4 radd3 radd2 radd1 radd0 mode 1 mode 0 writing to control register 1 to set adc channel, mode, and read register address adc channel address 5-bit read register address operating mode extended write address control register 1 address normal (single-ended)/ ratiometric (differential) conversion f i g u re 45. d e s i g n at ion of d a t a -w o r d b i t s in a d 78 7 7 writ e o p er at io ns 0 3796-025 dclk dout 1 din 2 cs notes: 1 data is clocked out on the falling edge of dclk. 2 input data is sampled on the rising edge of dclk. 3 for 8-bit registers, 8 leading zeros precede 8 bits of data. 4 register read address increments automatically, provided that a new address is not written to control register 1. high-z high-z 11 6 1 register n + 1 data 4 register n data 4 0000 + 12-bit data 3 0000 + 12-bit data 3 4-bit address + 12-bit data d15 d0 d15 d0 d15 d0 1 6 f i g u re 46. o v er a ll r e ad/ w r i te tim i ng
ad7877 rev. a | page 29 of 44 write timing no serial interface operations can take place while cs is high. to write to the ad7877, cs must be taken low. to write to the device, a burst of 16 clock pulses is input to dclk while the write data is input to din. data is clocked in on the rising edge of dclk. if multiple write operations are to be performed, cs must be taken high after the end of each write operation before another write operation can be performed by taking cs low again. reading data data is available on the dout pin following the falling edge of cs , when the device is being clocked. the msb is clocked out on the falling edge of cs , with subsequent data bits clocked out on the falling edge of dclk. after cs is taken low and the device is clocked, the ad7877 outputs data from the register whose read address is currently stored in control register 1. once this data has been output, the address increments automatically. cs must be taken high between reads. when cs is taken low again, reading continues from the register whose read address is in control register 1, provided that a write operation does not change the address. if the register read address reaches 11111b, it is then reset to zero. this feature allows all registers to be read out in sequence without having to explicitly write all their addresses to the device. note that because data-words are 16 bits long, but the data registers are only 12 bits long, or 8 bits in the case of gpio registers, the first four bits of a readback data-word are zeros, or the first 8 bits in the case of a gpio register. v drive pin the supply voltage to all pins associated with the serial interface ( dav , din, dout, dclk, cs , penirq , and alert ) is separate from the main v cc supply and is connected to the v drive pin. this allows the ad7877 to be connected directly to processors whose supply voltage is less than the minimum operating voltage of the ad7877, in fact, as low as 1.7 v.
ad7877 rev. a | page 30 of 44 general-purpose i/o pins the ad7877 has one dedicated general-purpose logic input/ output pin (gpio4), and any or all of the three auxiliary analog inputs can also be reconfigured as gpios. associated with the gpios are two 8-bit control registers and one 8-bit data register, which are accessed using the extended write mode. as mentioned previously, gpio registers are written to using the extended writing mode. the first four bits of the data-word must be 1111b to access the extended writing map, and the next four bits are the gpio register address. this leaves 8 bits for the gpio register data, because all gpio registers are 8 bits. the gpio control registers are located at extended writing map addresses 0000b and 0001b, and the gpio data register is at address 0010b. gpio registers are read in the same way as other registers, by writing a 5-bit address to control register 1. the gpio registers are located at read addresses 11011b to 11101b. gpio configuration each gpio pin is configured by four bits in one of the gpio control registers and has a data bit in the gpio data register. the gpio configuration bits are described in the following sections and in table 12. also see the detailed register descriptions section. enableen these bits enable or disable the gpio pins. when en = 0, the corresponding gpio pin is configured as the alternate function (aux input). the other gpio configuration bits have no effect, if the particular gpio is not enabled. when en = 1, the pin is configured as a gpio pin. gpio4, which does not have an alternate function, does not have an en bit; it is always enabled. directiondir these bits set the direction of the gpio pins. when dir = 0, the pin is an output. setting or clearing the relevant bit in the gpio data register outputs a value on the corresponding gpio pin. the output value depends on the pol bit. when dir = 1, the pin is an input. an input value on the relevant gpio pin sets or clears the corresponding bit in the gpio data register, depending on the pol bit. a gpio data register bit is read-only when dir = 1 for that gpio. polaritypol when pol = 0, the gpio pin is active low. when pol = 1, the gpio pin is active high. how this bit affects the gpio opera- tion also depends on the dir bit. if pol = 1 and dir = 1, a 1 at the input pin sets the corre- sponding gpio data register bit to 1. a 0 at the input pin clears the corresponding gpio data bit to 0. if pol = 1 and dir = 0, a 1 in the gpio data register bit puts a 1 on the corresponding gpio output pin. a 0 in the gpio data register bit puts a 0 on the gpio output pin. if pol = 0 and dir = 1, a 1 at the input pin sets the corre- sponding gpio data bit to 0. a 0 at the input pin clears the corresponding gpio data bit to 1. if pol = 0 and dir = 0, a 1 in the gpio data register bit puts a 0 on the corresponding gpio output pin. a 0 in the gpio data register bit puts a 1 on the gpio output pin. alert enablealen gpios can operate as interrupt sources to trigger the alert output. this is controlled by the alert enable (alen) bits in the gpio configuration registers. when alen = 1, the correspond- ing gpio can trigger an alert . when alen = 0, the corre- sponding gpio cannot cause the alert output to assert. alert is asserted low, if any gpio data register bit is set when the gpio is configured as an input. the gpio data bit is set, if a 1 appears on the gpio input pin when pol = 1, or if a 0 appears on the gpio input pin when pol = 0. note that alert is triggered only when the gpio is configured as an input, that is, when dir = 1. alert can never be triggered by a gpio that is configured as an output, that is, dir = 0. alert output the alert pin is an alarm or interrupt output that goes low, if any one of a number of interrupt sources is asserted. the results of high and low limit comparisons on the aux1, bat1, bat2, and temp1 channels are interrupt sources. an out-of-limit comparison sets a status bit in the alert status/mask register (address 00011b).there are separate status bits for both the high and low limits on each channel to indicate which limit was exceeded. the interrupt sources can be masked out by clearing the corresponding enable bit in this register. there is one enable bit per channel. alert is also asserted, if an input on a gpio pin sets a bit in the gpio data register, as explained in the previous section. gpio interrupts can be disabled by clearing the corresponding alen bit in the gpio control registers. the interrupt source can be identified by reading the gpio data register and the alert status/enable register. alert remains asserted until the source of the interrupt has been masked out or removed. if the alert source is a gpio, then masking out the interrupt by clearing the corresponding alen bit to 0 or removing the source of the interrupt on the gpio pin causes alert to go high again.
ad7877 rev. a | page 31 of 44 if the alert source is an out-of-limit measurement, writing a 0 to the corresponding status bit in the alert status/enable register causes alert to go high. however, the status bit is set to 1 again on the next measurement cycle, if the measurement remains out of limit. the alert source can also be masked by clearing the relevant bit in the alert status/enable register to 0. table 12. gpio configuration en dir pol alen data bit 1 pin voltage 2 alert 0 x x x x x x 1 0 0 0 0 1 1 1 0 0 0 1 0 1 1 0 0 1 0 1 1 1 0 0 1 1 0 1 1 0 1 0 0 0 1 1 0 1 0 1 1 1 1 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 0 0 1 0 1 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 1 1 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 1 shaded data values indicate that a change in input voltage on the pin causes a change in the data register bit. 2 shaded pin voltage values indicate that a change in the data register causes a change in the output voltage on the pin.
ad7877 rev. a | page 32 of 44 groundi ng a nd la yout i t is r e co mme nde d t h a t t h e g r oun d p i n s , a g n d an d d g nd , b e s h o r t e d t o g e t h er as c l os e as p o ssi b l e t o t h e de vice i t s e lf o n t h e us er s pcb . f o r m o r e info r m a t ion o n g r o u n d in g and l a yo u t co n s idera t io n s f o r th e ad7877, r e f e r t o th e l a y out a n d grou n d ing r e c o m m e n - d a tio n s fo r t o uc h s c r e en d i g i ti z e rs t e c h n i ca l n o t e . pcb desig n guideline s for chip sc ale pa c k a g e s the lan d s on t h e chi p s c ale p a cka g e (c p - 32) a r e r e c t a n gu la r . the p r in te d cir c ui t b o a r d p a d for t h es e sh o u ld b e 0.1 mm lo n g e r th a n th e pa c k a g e la n d len g th a n d 0. 05 m m w i d e r th a n t h e p a cka g e land w i d t h. th e l a nd sh o u ld b e ce n t er e d o n t h e p a d . this ens u r e s tha t t h e s o lder jo in t size is maximize d . the b o t t o m o f t h e chi p s c ale p a cka g e has a ce n t ral t h er mal p a d . the t h er mal p a d o n t h e p r in t e d cir c ui t b o a r d sh o u ld b e a t le ast a s la r g e a s th i s exposed pa d . on th e p r i n t e d ci r c ui t boa r d , th e r e s h o u ld b e a cle a ra n c e o f a t le as t 0.25 mm b e tw e e n t h e t h er mal p a d an d t h e in ner e d ges o f t h e p a d p a t t er n. thi s en sur e s t h a t shor t i ng i s a v oi d e d. ther ma l v i as can b e us e d on t h e p r in te d cir c ui t b o a r d t h er ma l p a d t o im p r o v e t h er mal p e r f o r ma nce o f t h e p a cka g e . i f vi as a r e used , th ey s h o u l d b e in co r p o r a t ed in th e th e r m a l pa d a t a 1.2 mm p i t c h g r id . th e via diamet er s h o u ld b e b e tw een 0.3 mm a nd 0.33 mm and the via ba r r e l s h o u ld b e p l a t e d wi th 1 oz. co p p er t o pl ug t h e v i a . the us er sho u ld co nne c t t h e p r i n te d cir c ui t b o ar d t h er ma l p a d to a g nd . 03796-026 host nc = no connect ad7877 24 nc 21 gpio4 20 stopacq 19 din 17 penirq 18 cs 22 alert 23 dav nc 1 bat2 2 bat1 3 aux3/gpio3 4 aux2/gpio2 5 aux1/gpio1 6 v cc 7 nc 8 nc 32 v re f 31 aout 30 arng 29 v driv e 28 dout 27 dclk 26 nc 25 nc 9 x? 10 y? 11 x+ 12 y+ 13 agnd 14 dgnd 15 nc 16 int1 spi inte rface int2 sclk miso mosi penirq cs gpio hsync signal from lcd v cc r rng 0.1 f dc-dc converter v in out fb to lcd backlight touch screen 0.1 f 1.0 f?10 f (optional) voltage regulator temperature measurement diode main battery secondary battery from audio remote control from hotsync inputs f i gure 47. t y pic a l a p plic at ion cir c u i t
ad7877 rev. a | page 33 of 44 register maps table 13. write register map register address binary wadd3 wadd2 wadd1 wadd0 hex register name description 0 0 0 0 0 none unused. writing to this address has no effect. 0 0 0 1 1 control register 1 contains adc channel address, register read address, and adc mode. 0 0 1 0 2 control register 2 contains adc averaging, acquisition time, power manage- ment, first conversion delay, stopacq polarity, and reference and timer settings. 0 0 1 1 3 alert status/enable register contains status of high/low l imit comparisons for temp1, bat1, bat2, and aux1, and enable bits to allow these channels to become interrupt sources. 0 1 0 0 4 aux1 high limit user-programmable aux1 upper limit. 0 1 0 1 5 aux1 low limit user-programmable aux1 lower limit. 0 1 1 0 6 bat1 high limit user-programmable bat1 upper limit. 0 1 1 1 7 bat1 low limit user-programmable bat1 lower limit. 1 0 0 0 8 bat2 high limit user-programmable bat2 upper limit. 1 0 0 1 9 bat2 low limit user-programmable bat2 lower limit. 1 0 1 0 a temp1 low limit user-programmable temp1 lower limit. 1 0 1 1 b temp1 high limit user-programmable temp1 upper limit. 1 1 0 0 c sequencer register 0 contains channel selection data for slave mode (software) sequencing. 1 1 0 1 d sequencer register 1 contains channel selection data for master mode (hardware) sequencing. 1 1 1 0 e dac register cont ains dac data and setup information. 1 1 1 1 f extended write not a physical register. enables writing to extended writing map. table 14. extended writing map register address binary eadd3 eadd2 eadd1 eadd0 hex register name description 0 0 0 0 0 gpio control register 1 contains polarity, direction, enabling, and interrupt enabling settings for gpio1 and gpio2. 0 0 0 1 1 gpio control register 2 contains polarity, direction, enabling, and interrupt enabling settings for gpio3 and gpio4. 0 0 1 0 2 gpio data contains gpio1 to gpio4 data.
ad7877 rev. a | page 34 of 44 table 15. read register map register address binary radd4 radd3 radd2 radd1 radd0 hex register name description 0 0 0 0 0 00 none reads back all zeros. 0 0 0 0 1 01 control register 1 see table 13. 0 0 0 1 0 02 control register 2 see table 13. 0 0 0 1 1 03 alert status/enable register see table 13. 0 0 1 0 0 04 aux1 high limit see table 13. 0 0 1 0 1 05 aux1 low limit see table 13. 0 0 1 1 0 06 bat1 high limit see table 13. 0 0 1 1 1 07 bat1 low limit see table 13. 0 1 0 0 0 08 bat2 high limit see table 13. 0 1 0 0 1 09 bat2 low limit see table 13. 0 1 0 1 0 0a temp1 low limit see table 13. 0 1 0 1 1 0b temp1 high limit see table 13. 0 1 1 0 0 0c sequencer register 0 see table 13. 0 1 1 0 1 0d sequencer register 1 see table 13. 0 1 1 1 0 0e dac register see table 13. 0 1 1 1 1 0f none factory use only. 1 0 0 0 0 10 x+ measurem ent at x+ input for y position. 1 0 0 0 1 11 y+ measurement at y+ input for x position. 1 0 0 1 0 12 y? (z2) measurement at y? input for touch-pressure calculation z2. 1 0 0 1 1 13 aux1 auxiliary input 1 measurement. 1 0 1 0 0 14 aux2 auxiliary input 2 measurement. 1 0 1 0 1 15 aux3 auxiliary input 3 measurement. 1 0 1 1 0 16 bat1 battery input 1 measurement. 1 0 1 1 1 17 bat2 battery input 1 measurement. 1 1 0 0 0 18 temp1 single-ended temperature measurement. 1 1 0 0 1 19 temp2 differential temperature measurement. 1 1 0 1 0 1a x+ (z1) measurement at x+ input for touch-pressure calculation z1. 1 1 0 1 1 1b gpio control register 1 see table 13. 1 1 1 0 0 1c gpio control register 2 see table 13. 1 1 1 0 1 1d gpio data register see table 13. 1 1 1 1 0 1e none factory use only. 1 1 1 1 1 1f none factory use only.
ad7877 rev. a | page 35 of 44 detailed register descriptions register name: control register 1 write address: 0001; read address: 00001; default value: 0x000; type: read/write. table 16. bit name read/ write description 0 mode0 r/w lsb of adc mode code 1 mode1 r/w msb of adc mode code 00 = no conversion 01 = single conversion 10 = conversion sequence (slave mode) 11 = conversion sequence (master mode) 2 rd0 r/w lsb of register read address. to read a regist er, its address must first be written to control register 1. 3 rd1 r/w bit 1 of register read address. to read a regist er, its address must first be written to control register 1. 4 rd2 r/w bit 2 of register read address. to read a regist er, its address must first be written to control register 1. 5 rd3 r/w bit 3 of register read address. to read a regist er, its address must first be written to control register 1. 6 rd4 r/w msb of register read address. to read a regist er, its address must first be written to control register 1. 7 chadd0 r/w lsb of adc channel address 8 chadd1 r/w bit 1 of adc channel address 9 chadd2 r/w bit 2 of adc channel address 10 chadd3 r/w msb of adc channel address 0000 = x+ input (y position) 0001 = y+ input (x position) 0010 = y? (z2) input (used for to uch-pressure calculation) 0011 = auxiliary input 1 (aux1) 0100 = auxiliary input 2 (aux2) 0101 = auxiliary input 3 (aux3) 0110 = battery monitor input 1 (bat1) 0111 = battery monitor input 2 (bat2) 1000 = temperature measurement 1 (used for single conversion) 1001 = temperature measurement 2 (used for differential measurement method) 1010 = x+ (z1) input (used for to uch-pressure calculation) 11 ser/ dfr r/w selects normal (single-ended) or ratiometric (differential) conversion 0 = ratiometric (differential) 1 = normal (single-ended)
ad7877 rev. a | page 36 of 44 register name: control register 2 write address: 0010; read address: 00010; default value: 0x000. table 17. bit name read/ write description 0 tmr0 r/w lsb of conversion interval timer 1 tmr1 r/w msb of conversion interval timer 00 = convert only once 01 = every 1024 clock periods (512 s) 10 = every 2048 clock periods (1.024 ms) 11 = every 16384 clock periods (8.19 ms) 2 ref r/w selects internal or external reference 0 = internal reference 1 = external reference 3 pol r/w indicates polarity of signal on stopacq pin 0 = active low 1 = active high 4 fcd0 r/w lsb of first conversion delay 5 fcd1 r/w msb of first conversion delay this delay occurs before the first conversion after powering up the adc, before converting the x and y coordinate channels to allow settling, and after the last conversion to allow penirq precharge. 00 = 1 clock period delay (500 ns) 01 = 256 clock periods delay (128 s) 10 = 2048 clock periods delay (1.024 ms) 11 = 16384 clock periods delay (8.19 ms) 6 pm0 r/w lsb of adc power management code 7 pm1 r/w msb of adc power management code 00 = adc and reference powered down continuously 01 = adc and reference* powered down when not converting 10 = adc and reference* powered up continuously 11 = adc powered down when not con verting, reference* powered up *irrespective of pm bits, reference is al ways powered down, if ref bit is 1. 8 acq0 r/w lsb of adc acquisition time 9 acq1 r/w msb of adc acquisition time 00 = 4 clock periods (2 s) 01 = 8 clock periods (4 s) 10 = 16 clock periods (8 s) 11 = 32 clock periods (16 s) 10 avg0 r/w lsb of adc averaging code 11 avg1 r/w msb of adc averaging code 00 = no averaging (1 conversion per channel) 01 = 4 measurements per channel averaged 10 = 8 measurements per channel averaged 11 = 16 measurements per channel averaged
ad7877 rev. a | page 37 of 44 register name: alert status/enable register write address: 0011; read address: 00011; default value: 0x000. table 18. bit name read/ write description 0 aux1lo r/w when this bit is 1, the aux1 channel is below its low limit. 1 bat1lo r/w when this bit is 1, the bat1 channel is below its low limit. 2 bat2lo r/w when this bit is 1, the bat2 channel is below its low limit. 3 temp1hi r/w when this bit is 1, th e temp1 channel is below its high limit. 4 aux1hi r/w when this bit is 1, th e aux1 channel is above its high limit. 5 bat1hi r/w when this bit is 1, th e bat1 channel is above its high limit. 6 bat2hi r/w when this bit is 1, th e bat2 channel is above its high limit. 7 temp1lo r/w when this bit is 1, the temp1 channel is above its low limit. 8 aux1en r/w setting this bit enables aux1 as an interrupt source to the alert output. 9 bat1en r/w setting this bit enables bat1 as an interrupt source to the alert output. 10 bat2en r/w setting this bit enables bat2 as an interrupt source to the alert output. 11 temp1en r/w setting this bit enables temp1 as an interrupt source to the alert output. register name: aux1 high limit write address: 0100; read address: 00100; default value: 0x000; type: read/write. this register contains the 12-bit high limit for auxiliary input 1. register name: aux1 low limit write address: 0101; read address: 00101; default value: 0x000; type: read/write. this register contains the 12-bit low limit for auxiliary input 1. register name: bat1 high limit write address: 0110; read address: 00110; default value: 0x000; type: read/write. this register contains the 12-bit high limit for battery monitoring input 1. register name: bat1 low limit write address: 0111; read address: 00111; default value: 0x000; type: read/write. this register contains the 12-bit low limit for battery monitoring input 1. register name: bat2 high limit write address: 1000; read address: 01000; default value: 0x000; type: read/write. this register contains the 12-bit high limit for battery monitoring input 2. register name: bat2 low limit write address: 1001; read address: 01001; default value: 0x000; type: read/write. this register contains the 12-bit low limit for battery monitoring input 2. register name: temp1 low limit write address: 1010; read address: 01010; default value: 0x000; type: read/write. this register contains the 12-bit low limit for temperature measurement. register name: temp1 high limit write address: 1011; read address: 01011; default value: 0x000; type: read/write. this register contains the 12-bit high limit for temperature measurement.
ad7877 rev. a | page 38 of 44 register name: sequencer register 0 write address: 1100; read address: 01100; default value: 0x000. table 19. bit name read/ write description 0 not used r/w th is bit is not used. 1 z1_ss r/w setting this bit includes the z1 touch-pr essure measurement (x+ input) in a slave mode sequence. 2 temp2_ss r/w setting this bit includ es a temperature measurement using differential conversion in a slave mode sequence. 3 temp1_ss r/w setting this bit includes a temperature measuremen t using single-ended conversion in a slave mode sequence. 4 bat2_ss r/w setting this bit includes measurement of battery moni tor input 2 in a slave mode sequence. 5 bat1_ss r/w setting this bit includes measurement of battery moni tor input 1 in a slave mode sequence. 6 aux3_ss r/w setting this bi t includes measurement of auxiliar y input 3 in a slave mode sequence. 7 aux2_ss r/w setting this bi t includes measurement of auxiliar y input 2 in a slave mode sequence. 8 aux1_ss r/w setting this bi t includes measurement of auxiliar y input 1 in a slave mode sequence. 9 z2_ss r/w setting this bit includes the z2 touch-pres sure measurement (y? input) in a slave mode sequence. 10 xpos_ss r/w setting this bit includes measuremen t of the x position (y+ input) in a slave mode sequence. 11 ypos_ss r/w setting this bit includes measuremen t of the y position (x+ input) in a slave mode sequence. register name: sequencer register 1 write address: 1101; read address: 01101; default value: 0x000. table 20. bit name read/ write description 0 not used r/w th is bit is not used. 1 z1_ms r/w setting this bit includ es the z1 touch-pressure measurement (x+ input) in a master mode sequence. 2 temp2_ms r/w setting this bit includes a temper ature measurement using differential conversion in a master mode sequence. 3 temp1_ms r/w setting this bit includes a temper ature measurement using single-ended conversion in a master mode sequence. 4 bat2_ms r/w setting this bit in cludes measurement of battery monitor input 2 in a master mode sequence. 5 bat1_ms r/w setting this bit in cludes measurement of battery monitor input 1 in a master mode sequence. 6 aux3_ms r/w setting this bit includes measurement of auxiliary in put 3 in a master mode sequence. 7 aux2_ms r/w setting this bit includes measurement of auxiliary in put 2 in a master mode sequence. 8 aux1_ms r/w setting this bit includes measurement of auxiliary in put 1 in a master mode sequence. 9 z2_ms r/w setting this bit includ es the z2 touch-pressure measurement (y? input) in a master mode sequence. 10 xpos_ms r/w setting this bit incl udes measurement of the x position (y+ input) in a master mode sequence. 11 ypos_ms r/w setting this bit incl udes measurement of the y position (x+ input) in a master mode sequence.
ad7877 rev. a | page 39 of 44 register name: dac register write address: 1110; read address: 01110; default value: 0x000. table 21. bit name read/ write description 0 range r/w output range of the dac in voltage mode 0 = 0 to v cc /2 1 = 0 to v cc 1 not used r/w th is bit is not used. 2 v/i r/w voltage output and current output 0 = voltage 1 = current 3 pd r/w dac power-down 0 = dac on 1 = dac powered down 4 dac0 lsb of dac data 5 dac1 bit 1 of dac data 6 dac2 bit 2 of dac data 7 dac3 bit 3 of dac data 8 dac4 bit 4 of dac data 9 dac5 bit 5 of dac data 10 dac6 bit 6 of dac data 11 dac7 msb of dac data register name: y position write address: n/a; read address: 10000; default value: 0x000; type: read only. this register contains the 12-bit result of the measurement at the x+ input with y layer excited (y position measurement). register name: x position write address: n/a; read address: 10001; default value: 0x000; type: read only. this register contains the 12-bit result of the measurement at the y+ input with x layer excited (x position measurement). register name: z2 write address: n/a; read address: 10010; default value: 0x000; type: read only. this register contains the 12-bit result of the measurement at the y? input with excitation voltage applied to y+ and x? (used for touch- pressure calculation). register name: aux1 write address: n/a; read address: 10011; default value: 0x000; type: read only. this register continues the 12-bit result of the measurement at auxiliary input 1. register name: aux2 write address: n/a; read address: 10100; default value: 0x000; type: read only. this register continues the 12-bit result of the measurement at auxiliary input 2. register name: aux3 write address: n/a; read address: 10101; default value: 0x000; type: read only. this register continues the 12-bit result of the measurement at auxiliary input 3.
ad7877 rev. a | page 40 of 44 register name: bat1 write address: n/a; read address: 10110; default value: 0x000; type: read only. this register continues the 12-bit result of the measurement at battery monitor input 1. register name: bat2 write address: n/a; read address: 10111; default value: 0x000; type: read only. this register continues the 12-bit result of the measurement at battery monitor input 2. register name: temp1 write address: n/a; read address: 11000; default value: 0x000; type: read only. this register continues the 12-bit result of a temperature measurement using single-ended conversion. register name: temp2 write address: n/a; read address: 11001; default value: 0x000; type: read only. this register continues the 12-bit result of a temperature measurement using a differential conversion. register name: z1 write address: n/a; read address: 11010; default value: 0x000; type: read only. this register continues the 12-bit result of a measurement at the x+ input with excitation voltage applied to y+ and x? (used f or touch- pressure calculation).
ad7877 rev. a | page 41 of 44 gpio registers gpio registers are written to using an extended 8-bit address. the first four bits of the data-word are always 1111b to access the extended writing map. the next four bits are the register address. this leaves 8 bits for the gpio data. gpio registers are read like all other registers, by writing a 5-bit address to control register 1, then reading dout. see the gpio configuration section for information on configuring the gpios. register name: gpio control register 1 write address: [1111] 0000; read address: 11011; default value: 0x000. table 22. bit name read/ write description 0 gpio2_alen r/w if this bit is 1, gpio2 is an interrupt source for the alert output. clearing this bit masks out gpio2 as an interrupt source for the alert output. 1 gpio2_dir r/w this bit sets the direction of gpio2. 0 = output 1 = input 2 gpio2_pol r/w this bit determin es if gpio2 is active high or low. 0 = active low 1 = active high 3 gpio2_en r/w this bit selects the function of aux2/gpio2. 0 = aux2 1 = gpio2 4 gpio1_alen r/w if this bit is 1, gpio1 is an interrupt source for the alert output. clearing this bit masks out gpio1 as an interrupt source for the alert output. 5 gpio1_dir r/w this bit sets the direction of gpio1. 0 = output 1 = input 6 gpio1_pol r/w this bit determin es if gpio1 is active high or low. 0 = active low 1 = active high 7 gpio1_en r/w this bit selects the function of aux1/gpio1. 0 = aux1 1 = gpio1
ad7877 rev. a | page 42 of 44 register name: gpio control register 2 write address: [1111] 0001; read address: 11100; default value: 0x000. table 23. bit name read/ write description 0 gpio4_alen r/w if this bit is 1, gpio4 is an interrupt source for the alert output. clearing this bit masks out gpio3 as an interrupt source for the alert output. 1 gpio4_dir r/w this bit sets the direction of gpio4. 0 = output 1 = input 2 gpio4_pol r/w this bit determin es if gpio4 is active high or low. 0 = active low 1 = active high 3 not used this bit is not used. 4 gpio3_alen r/w if this bit is 1, gpio3 is an interrupt source for the alert output. clearing this bit masks out gpio4 as an interrupt source for the alert output. 5 gpio3_dir r/w this bit sets the direction of gpio3. 0 = output 1 = input 6 gpio3_pol r/w this bit determin es if gpio3 is active high or low. 0 = active low 1 = active high 7 gpio3_en r/w this bit selects the function of aux3/gpio3. 0 = aux3 1 = gpio3 register name: gpio data register write address: [1111] 0010; read address: 11101; default value: 0x000. table 24. bit name read/ write description 0 not used this bit is not used. 1 not used this bit is not used. 2 not used this bit is not used. 3 not used this bit is not used. 4 gpio4_dat r/w gpio4 data bit. 5 gpio3_dat r/w gpio3 data bit. 6 gpio2_dat r/w gpio2 data bit. 7 gpio1_dat r/w gpio1 data bit.
ad7877 rev. a | page 43 of 44 outline dimensions compliant to jedec standards mo-220-vhhd-2 0.30 0.23 0.18 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 12 max 1.00 0.85 0.80 seating plane coplanarity 0.08 1 32 8 9 25 24 16 17 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indicato r top view 5.00 bsc sq 4.75 bsc sq 3.25 3.10 sq 2.95 pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (b o t t om view) f i gure 48. 3 2 -l ead l e ad f r a m e ch ip s c a l e p a ck ag e [l fc sp ] 5 mm 5 m m b o d y (c p - 3 2 - 2 ) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model operating temperature rang e package descri ption package option ad7877acp-re el ?40c to +85c 32-lead lfcsp cp-32-2 ad7877acp-re el7 ?40c to +85c 32-lead lfcsp cp-32-2 ad7877acp-50 0 rl7 ?40c to +85c 32-lead lfcsp cp-32-2 ad7877acpz-reel 1 ?40c to +85c 32-lead lfcsp cp-32-2 ad7877acpz-r eel7 1 ?40c to +85c 32-lead lfcsp cp-32-2 ad7877acpz-5 00rl7 1 ?40c to +85c 32-lead lfcsp cp-32-2 eval-ad7877 eb evaluation boar d 1 z = pb-free part.
ad7877 rev. a | page 44 of 44 notes ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . d03796C0C 11/04(a)

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